P
US6081133AExpiredUtilityPatentIndex 74

Universal receiver device

Assignee: ERICSSON TELEFON AB L MPriority: Nov 10, 1995Filed: May 7, 1998Granted: Jun 27, 2000
Est. expiryNov 10, 2015(expired)· nominal 20-yr term from priority
Inventors:HEDBERG MATS
H04L 25/0292H03K 19/018528H04L 25/0276H03K 19/0175
74
PatentIndex Score
7
Cited by
12
References
3
Claims

Abstract

A receiver device includes two input circuits, connected in parallel, for receiving digital information in the form of electrical differential binary signals within a broad range of common-mode voltages. The input circuits in turn include transistors in differential input arrangements for receiving the signals. The transistors of input circuits are of one and the same type, so that the receiver device is capable of handling higher speeds. Controlled activation and deactivation of a first one of the input circuits further enhances the speed capabilities of the receiver device.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A receiver device comprising an input stage for receiving a differential signal at its inputs, a driver stage and an output stage, said input stage in turn comprising a first input circuit, and a second input circuit connected in parallel, said first input circuit comprising first transistors for directly receiving signals from outside said receiver device, said second input circuit comprising second transistors for directly receiving signals from outside said receiver device, wherein said first transistors and said second transistors are of one and the same type, and   one of said first transistors is comprised in a first current mirror, and another one of said first transistors is comprised in a second current mirror,   whereby said receiver device is capable of high speed operation over a wide common-mode range.   
     
     
       2. A receiver device according to claim 1, wherein said first current mirror and said second current mirror comprise cascode-connected transistors for achieving low error in a chain of current mirrors in the receiver device, whereby error multiplication is reduced. 
     
     
       3. A receiver device according to claim 1, wherein said second input circuit comprises transistors connected for shunting a current so as to maintain a constant aggregate current through load circuit-elements for common-mode voltages at the inputs within an entire common-mode range, whereby propagation delay through said receiver device is substantially independent of said common-mode voltages.

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References (0)

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