Apparatus for improving linearity of small signal

Abstract

An apparatus for improving linearity of small signal according to the present invention comprises a least of one non-linear signal generating means for receiving a first DC bias larger than a threshold voltage and for generating a non-linear signal; feedback means for returning the non-linear signal from said a least of one non-linear signal generating means; and amplifying means for receiving, amplifying and outputting to an output unit, a second DC bias larger than the threshold voltage and a reversed and feedback non-linear signal such that the non-linear signal is cancelled. The linearizers according to the present invention have a higher linearity and a simple constitution, and thereby being used for various terminals.

What is claimed is: 
     
       1. An apparatus for improving linearity of small signal comprising: a least of one non-linear signal generating means for receiving a DC bias larger than a threshold voltage and for generating a non-linear signal;   feedback means for returning the non-linear signal from said non-linear signal generating means; and   amplifying means for receiving a first DC bias larger than the threshold voltage and the non-linear signal such that the non-linear signal is cancelled.   
     
     
       2. The apparatus as claimed in claim 1, wherein said amplifying means comprises: a first DC signal blocking means for blocking DC signal of an input signal and transferring only an AC signal of the input signal;   a first input signal leakage prevention means for transferring the first DC bias and for preventing leak of an output signal from the first DC signal blocking means; and   an amplifier for receiving the first DC bias from said first input signal leakage prevention means, and for amplifying and outputting to an output unit the input signal from the first input signal leakage prevention means.   
     
     
       3. The apparatus as claimed in claim 2, wherein said amplifier comprises a first NMOS transistor of which a source is connected to a ground, a gate is connected to said first DC signal blocking means and said first input signal leakage prevention means and a drain is connected to said output means, for amplifying the input signal from the first input signal leakage prevention means. 
     
     
       4. The apparatus as claimed in claim 3, wherein said non-linear signal generating means comprises a first and a second non-linear signal generating means each of which is connected to said amplifying means in parallel. 
     
     
       5. The apparatus as claimed in claim 4, wherein said non-linear signal generating means comprises: a second DC signal blocking means for blocking the DC signal of the input signal and for transferring only the AC signal of the input signal;   a second input signal leakage prevention means for transferring the second DC bias and for preventing leak of output signal from said second DC signal blocking means; and   non-linear signal generating means for receiving the first DC bias from a second input signal leakage prevention means and for outputting to said feedback means the non-linear signal having the same phase as that of the amplified signal outputted from said amplifying means.   
     
     
       6. The apparatus as claimed in claim 5, wherein said non-linear signal generating means comprises a second NMOS transistor of which a source is connected to the ground, a gate is connected to said second DC signal blocking means and said second input signal leakage prevention means and a drain is connected to said feedback means, for receiving the second DC bias from said second input signal leakage prevention means, and for outputting to said feedback means the non-linear signal having the same phase as the amplified non-linear signal from said amplifying means.   
     
     
       7. The apparatus as claimed in claim 6, wherein said first DC signal blocking means comprises a first capacitance of which one end is connected to said input means and the other end is to the gate of the first NMOS transistor. 
     
     
       8. The apparatus as claimed in claim 7, wherein said second DC signal blocking means comprises a second capacitance of which one end is connected to an input means and the other end is connected to the gate of the second NMOS transistor. 
     
     
       9. The apparatus as claimed in claim 8, wherein said first and said second input signal leakage prevention means each comprises a resistor and an inductor.