Image display for dither halftoning

Abstract

Disclosed is an image display apparatus for dither halftoning a video signal that enters from an external unit and displaying the resulting video signal on a display unit. A dither table, which comprises an array of dither threshold values used by a dither halftoning circuit, is changed based upon the capability of the display unit to display halftone display colors and/or data relating to the number of display colors contained in the video signal. In order to select threshold values, an output value of the dither halftoning circuit, which is at an identical display position in the immediately preceding frame of the video signals is referenced.

What is claimed is: 
     
       1. An image display apparatus for dither halftoning a video signal that enters from an external unit and displaying the resulting video signal on a display unit, comprising: a dither halftoning circuit converting the video signal to a dither output signal by using dither threshold values; and   an XY address control circuit generating X-direction and Y-direction address signals for specifying dither threshold values used in said dither halftoning circuit, said control circuit including: a Y-direction counter generating the Y-direction address signal by counting a horizontal synchronizing signal which is reset by a vertical synchronizing signal;   a multiplier doubling the generated Y-direction address signal;   an adder adding 1 to the doubled Y-direction address signal; and   a selector selecting, when the inputted video signal is an interlaced signal, the Y-direction address signal outputted from said multiplier or said adder on the basis of whether an odd- or even-numbered field signal is received by said selector.     
     
     
       2. The apparatus according to claim 1, wherein said XY address control circuit further includes a second adder adding value indicating an amount of movement in the Y-direction, which represents a changed capture position of the video signal, to the Y-direction address signal generated by said Y-direction counter and outputting the added Y-direction address signal to said multiplier. 
     
     
       3. The apparatus according to claim 1, wherein said XY address control circuit further includes a divider dividing an output address signal outputted from said selector by a size of a dither matrix in the Y direction and outputting a value of the remainder thereof to said dither halftoning circuit. 
     
     
       4. An image display apparatus for dither halftoning a video signal that enters from an external unit and displaying the resulting video signal on a display unit, comprising: a dither halftoning circuit converting the video signal to a dither output signal by using dither threshold values; and   an XY address control circuit generating X-direction and Y-direction address signals for specifying dither threshold values used in said dither halftoning circuit,   with said XY address control circuit including: an X-direction counter generating the X-direction address signal by counting a pixel clock signal which is reset by a horizontal synchronizing signal;   a multiplier doubling the generated X-direction address signal; and   an adder adding 1 to the doubled X-direction address signal, wherein     said XY address control circuit selects, when the inputted video signal is a demultiplexed signal, both the X-direction address signal of said multiplier and said adder.   
     
     
       5. The apparatus according to claim 4, wherein said XY address control circuit further includes a second adder adding value indicating an amount of movement in the X-direction, which represents a changed capture position of the video signal, to the X-direction address signal generated by said X-direction counter and outputting the added X-direction address signal to said multiplier. 
     
     
       6. The apparatus according to claim 4, with said XY address control circuit further including: a first divider dividing the output address signal outputted from said multiplier by a size of a dither matrix in the X direction and outputting the value of the remainder thereof to said dither halftoning circuit; and   a second divider dividing the output address signal outputted from said adder by a size of the dither matrix in the X direction and outputting the value of the remainder thereof to said dither halftoning circuit.