Integrated power supply voltage generators having reduced susceptibility to parasitic latch-up during set-up mode operation

Abstract

Integrated power supply voltage generators include a boosted voltage generator which generates a boosted voltage signal (Vpp) at a first level on a boosted voltage signal line during a set-up time interval, in response to an internal power supply voltage signal (VINTA*), and a circuit which is responsive to a first reference voltage (VREFA) and the boosted voltage signal (Vpp) and generates the internal power supply voltage signal (VINTA*) at a second level which is less than the first level throughout the set-up time interval.

That which is claimed is: 
     
       1. A circuit generating an internal power source voltage in a semiconductor memory device employing a boosted voltage, the circuit comprising: a comparing circuit having an input terminal connected to the internal power source voltage and an output terminal connected to a transistor which charges the internal power source voltage; and   a transistor connected between a reference voltage and another input of the comparing circuit.   
     
     
       2. A semiconductor memory device employing a boosted voltage, the device comprising: an internal circuit including a PMOS transistor whose source is connected to an internal power source voltage and whose bulk is connected to the boosted voltage;   a circuit for generating the internal power source voltage, including a comparing circuit having an input terminal connected to the internal power source voltage and an output terminal connected to a transistor which charges the internal power source voltage; and   a transistor connected between a reference voltage and another input of the comparing circuit.   
     
     
       3. An integrated power supply voltage generator, comprising: a boosted voltage generator which generates a boosted voltage signal at a first level on a boosted voltage signal line during a set-up time interval, in response to an internal power supply voltage signal; and   means, responsive to a first reference voltage and the boosted voltage signal, for generating the internal power supply voltage signal at a second level which is less than the first level throughout the set-up time interval.   
     
     
       4. The voltage generator of claim 3, wherein said generating means comprises: a loading circuit which generates at an output thereof a second reference voltage having a magnitude less than a magnitude of the first reference voltage, upon application of the first reference voltage and the boosted voltage signal thereto; and   a differential amplifier having a first input electrically coupled to the output of said loading circuit and a second input electrically coupled to an input of said boosted voltage generator.   
     
     
       5. The voltage generator of claim 4, wherein said loading circuit comprises a field effect transistor having a gate electrode which is electrically connected to the boosted voltage signal line and a source/drain region electrically connected to the first input of said differential amplifier. 
     
     
       6. The voltage generator of claim 4, further comprising an inverter having a PMOS transistor therein which is electrically coupled in series between the second input of said differential amplifier and an output of said inverter; and wherein a bulk region of the PMOS transistor is electrically connected to the boosted voltage signal line.