Semiconductor integrated circuit capable of realizing logic functions

Abstract

A semiconductor integrated circuit is constructed with composite pass-transistor logic circuits serving as elementary circuit units each including a plurality of pass-transistor logic trees and a multiple-input logic gate. A wide variety of logical operations, even complex opearations, can be efficiently expressed using the composite pass-transistor logic circuit, and the resultant logic circuit can operate at a high speed. Thus, the semiconductor integrated circuit of the present invention can realize various logic functions required for various users in an efficient fashion. The present invention is particularly useful when applied to a field-programmable gate array integrated circuit, since complex logical operations can be expressed in a simple and efficient fashion by the composite pass-transistor logic circuits. The gate array integrated circuit obtained in accordance with the present invention can operate at a high speed with low power consumption. The present invention also discloses a basic cell suitable for use in an integrated circuit in the form of a gate array, and more particularly, a programmable logic block for use in a field programmable gate array integrated circuit.

What is claimed is: 
     
       1. An integrated circuit for executing a plurality of logical operations comprising a plurality of logic circuits, each for receiving a plurality of input logic signals and for producing an output logic signal, each of the logic circuits comprising: at least two pass-transistor logic trees each having at least two input nodes for receiving at least two of the input logic signals and an intermediate output node for providing an intermediate logic signal, each of the pass-transistor logic trees comprising at least two pass transistors; and   a multiple-input logic gate having at least two intermediate input nodes each for receiving the intermediate logic signal from corresponding one of the pass-transistor logic trees, and an output node for providing the output logic signal produced by a selected one of the plurality of logical operations executed on the plurality of input logic signals.   
     
     
       2. The integrated circuit according to claim 1, wherein each of pass transistors has an input, an output and a control terminal; and   said at least two input nodes of each of the pass-transistor logic trees includes the control terminal of at least one of the pass transistors.   
     
     
       3. The integrated circuit according to claim 1, wherein at least one of the pass-transistor logic trees comprises at least two stages. 
     
     
       4. The integrated circuit according to claim 1, wherein said multiple-input logic gate is one of a NAND, a NOR, an AND and an OR gate. 
     
     
       5. The integrated circuit according to claim 1, wherein said multiple-input logic gate comprises a third intermediate input node in addition to the at least two intermediate input nodes, for receiving one of the input logic signals. 
     
     
       6. The integrated circuit according to claim 1, wherein said multiple-input logic gate is a multiple-input complementary logic gate; and   each of the logic circuits further comprises a suppressor of a static feedthrough current of the multiple-input complementary logic gate.   
     
     
       7. The integrated circuit according to claim 6, wherein said suppressor of static feedthrough current comprises means for restoring potentials of the intermediate output nodes of all the pass-transistor logic trees in response to the output logic signal of the multiple-input complementary logic gate. 
     
     
       8. The integrated circuit according to claim 6, wherein said multiple-input complementary logic gate is a multiple-input CMOS logic gate;   each of the pass transistors comprises a N channel MOS transistor; and   said suppressor of feedthrough current comprises P channel MOS transistors each provided for each of the pass-transistor logic trees for restoring a potential of the corresponding intermediate output node in response to the output logic signal of the multiple-input CMOS logic gate.   
     
     
       9. The integrated circuit according to claim 1, wherein each of the pass transistors comprises an input, an output and a control terminal; and   each of the pass-transistor logic trees comprises at least one pair pass-transistor element each including two of the pass transistors, the output terminals of the pass transistors in each pair pass-transistor element being coupled.   
     
     
       10. The integrated circuit according to claim 9, wherein each of the pair pass-transistor elements comprises an inverter for producing a complementary logic signal of a logic signal received by the control terminal of one of the pass transistors and for providing the complementary logic signal to the control terminal of the other one of the pass transistors. 
     
     
       11. The integrated circuit according to claim 1, wherein each of the pass transistors has an input, an output and a control terminal;   each of the pass transistors comprises a switching device having a first conduction type and a first driving capacity, and having an input terminal connected to the input terminal of the pass transistor, an output terminal connected to the output terminal of the pass transistor and a control terminal connected to the control terminal of the pass transistor;   each of the pass transistors further comprises an auxiliary switching device each having a second conduction type and a second driving capacity which is less than the first driving capacity;   each of the auxiliary switching devices having an input terminal connected to the input terminal of the corresponding switching device, an output terminal connected to the output terminal of the corresponding switching device, and a control terminal for receiving a complementary logic signal of a logic signal received by the control terminal of the corresponding switching device.   
     
     
       12. The integrated circuit according to claim 11, wherein said switching devices are N channel MOS transistors each having a first W/L ratio, and the auxiliary switching devices are P channel MOS transistors each having a second W/L ratio which is less than the first W/L ratio. 
     
     
       13. The integrated circuit according to claim 12, wherein each of the pass-transistor logic trees comprises at least one pair pass-transistor element each including a first and a second pass transistors selected from the at least two pass transistors, the output terminals of the pass transistors in each pair pass transistor element are coupled. 
     
     
       14. The integrated circuit according to claim 13, wherein each of the pair pass-transistor elements includes an inverter having an input and an output terminals, the input terminal of the inverter is connected to the control terminal of the switching device in the first pass transistor and to the control terminal of the auxiliary switching device in the second pass transistor, and the output terminal of the inverter is connected to the control terminal of the switching device in the second pass transistor and to the control terminal of the auxiliary switching device in the first pass transistor. 
     
     
       15. The integrated circuit according to claim 1, wherein said integrated circuit is a gate array integrated circuit comprising an array of basic cells formed on a surface of a semiconductor substrate, each of the basic cells comprising a plurality of switching devices, and each of the logic circuits is formed with switching devices selected from the plurality of switching devices in at least one of the basic cells. 
     
     
       16. The integrated circuit according to claim 15, wherein said gate array integrated circuit is a mask programmable gate array integrated circuit. 
     
     
       17. The integrated circuit according to claim 15, wherein said gate array integrated circuit is a field programmable gate array integrated circuit. 
     
     
       18. In an integrated circuit for executing a plurality of logical operations comprising a plurality of logic circuits each for receiving a plurality of input logic signals and for producing an output logic signal, a method of forming each of the logic circuits comprising the steps of: arranging pass transistors to form at least two pass-transistor logic trees each having at least two input nodes for receiving at least two of the plurality of input logic signals and an intermediate output node for providing an intermediate logic signal, each of the pass-transistor logic trees comprising at least two of the pass transistors; and   providing a multiple-input logic gate having at least two intermediate input nodes each for receiving the intermediate logic signal from corresponding one of the at least two pass transistor logic trees, and an output node for providing the output logic signal produced by a selected one of the plurality of logical operations executed on the plurality of input logic signals.   
     
     
       19. The method according to claim 18, wherein each of the pass transistors has an input, an output and a control terminal; and   said step of arranging arranges the pass transistors such that said at least two input nodes of each of the pass-transistor logic trees include the control terminal of at least one of the pass transistors.   
     
     
       20. The method according to claim 18, wherein said step of arranging forms the at least two pass-transistor logic trees such that at least one of the pass-transistor logic trees comprises at least two stages. 
     
     
       21. The method according to claim 18, wherein said step of providing provides the multiple-input logic gate having a third intermediate input node in addition to the at least two intermediate input nodes, for receiving one of the input logic signals. 
     
     
       22. The method according to claim 18, further comprising the step of forming the pass transistors, such that each of the pass transistors comprises a switching device having a first conduction type and a first driving capacity, and having an input terminal connected to the input terminal of the pass transistor, an output terminal connected to the output terminal of the pass transistor and a control terminal connected to the control terminal of the pass transistor; wherein each of the pass transistors further comprises an auxiliary switching device each having a second conduction type and a second driving capacity which is less than the first driving capacity;   each of the auxiliary switching devices having an input terminal connected to the input terminal of the corresponding switching device, an output terminal connected to the output terminal of the corresponding switching device, and a control terminal for receiving a complementary logic signal of a logic signal received by the control terminal of the corresponding switching device.   
     
     
       23. The method according to claim 22, wherein said switching devices are N channel MOS transistors having a first W/L ratio, and said auxiliary switching devices are P channel MOS transistors having a second W/L ratio which is less than the first W/L ratio. 
     
     
       24. The method according to claim 18, wherein said multiple-input logic gate is a multiple-input complementary logic gate; and   said method further comprising the step of providing a suppressor of a static feedthrough current of the multiple-input complementary logic gate.   
     
     
       25. The method according to claim 24, wherein said suppressor of static feedthrough current comprises means for restoring potentials of the intermediate output nodes of all the pass-transistor logic trees in response to the output logic signal of the multiple-input complementary logic gate. 
     
     
       26. In an integrated circuit for executing a plurality of logical operations comprising a plurality of logic circuits each for receiving a plurality of input logic signals and for executing a selected one of the plurality of logical operations, a method of executing each of the plurality of logical operations comprising the steps of: providing at least two pass-transistor logic trees of the logic circuit, each having at least two input nodes and an intermediate output node, each of the pass-transistor logic trees comprising at least two pass transistors;   providing a multiple-input logic gate of the logic circuit, having at least two intermediate input nodes and an output node;   inputting at least two of the input logic signals to the at least two input nodes of each of the pass-transistor logic trees, such that an intermediate logic signal is provided at the intermediate output node;   inputting each of the intermediate logic signals to corresponding one of the intermediate input nodes of the multiple-input logic gate, such that an output logic signal produced by the selected one of the plurality of logical operations executed on the plurality of input logic signals is provided at the output node.   
     
     
       27. The method according to claim 26, wherein each of the pass transistors has an input, an output and a control terminal; and   said step of providing the at least two pass-transistor logic trees is performed such that said at least two input nodes of each of the pass transistor logic trees include the control terminal of at least one the pass transistors.   
     
     
       28. The method according to claim 26, wherein said step of providing provides the at least two pass-transistor logic trees such that at least one of the pass-transistor logic trees comprises at least two stages. 
     
     
       29. The method according to claim 26, wherein said step of providing the multiple-input logic gate provides the logic gate having a third intermediate input node in addition to the at least two intermediate input nodes; and   said method further comprises the step of inputting one of the input logic signals to the third intermediate input nodes of the multiple-input logic gate.   
     
     
       30. The method according to claim 26, wherein said multiple-input logic gate is a multiple-input complementary logic gate; and   said method further comprises a step of suppressing a static feedthrough current of the multiple-input complementary logic gate.   
     
     
       31. The method according to claim 30, wherein said step of suppressing includes restoring potentials of the intermediate output nodes of all the pass-transistor logic trees in response to the output logic signal of the multiple-input complementary logic gate. 
     
     
       32. The method according to claim 26, wherein each of the pass transistors has an input, an output and a control terminal;   said step of providing at least two pass-transistor logic trees includes: providing switching devices each for each of the pass transistors, each of the switching devices having a first conduction type and a first driving capacity, and having an input terminal connected to the input terminal of the pass transistor, an output terminal connected to the output terminal of the pass transistor, and a control terminal connected to the control terminal of the pass transistor;   providing auxiliary switching devices each for each of the switching devices, each of the auxiliary switching devices having a second conduction type and a second driving capacity less than the first driving capacity, each of the auxiliary switching devices having an input terminal connected to the input terminal of the corresponding switching device, an output terminal connected to the output terminal of the corresponding switching device, and a control terminal; and   said method further comprises the step of inputting mutually complementary logic signals to control terminals of the switching device and the auxiliary switching device in each of the pass transistors.     
     
     
       33. The method according to claim 32, wherein said switching devices are N channel MOS transistors each having a first W/L ratio, and said auxiliary switching devices are P channel MOS transistors each having a second W/L ratio which is less than the first W/L ratio. 
     
     
       34. A programmable logic block for use in a field programmable gate array, comprising: a plurality of signal input terminals for receiving input logic signals;   at least two pair pass-transistor elements each having two input terminals, an output terminal and a control terminal;   a multiple-input logic gate having at least two intermediate input nodes and an output node; and   programmable interconnections for programmably arranging the pair pass-transistor elements and the multiple-input logic gate,   wherein the programmable interconnections include at least two input signal interconnections each for connecting the control terminal of one of the pair pass-transistor elements to at least one of the signal input terminals.   
     
     
       35. The programmable logic block according to claim 34, wherein each of said input signal interconnections include a fixed interconnection for directly connecting the control terminal of one of the pair pass-transistor elements to one of the signal input terminals. 
     
     
       36. The programmable logic block according to claim 34, wherein each of said input signal interconnections includes a plurality of programmable switches each for programmably connecting the control terminal of one of the pair pass-transistor elements to corresponding one of the signal input terminals. 
     
     
       37. The programmable logic block according to claim 34, wherein each of the pair pass-transistor elements comprises a first and a second pass transistor each having an input terminal connected to corresponding one of the input terminals of the pair pass-transistor element, an output terminal connected to the output terminal of the pair pass-transistor element, and a control terminal, the control terminal of the first pass transistor is connected to the control terminal of the pair pass-transistor element. 
     
     
       38. The programmable logic block according to claim 37, wherein each of the pair pass-transistor element further comprises an inverter having an input and an output terminal, the input terminal of the inverter is connected to the control terminal of the pair pass-transistor element and the output terminal of the inverter is connected to the control terminal of the second pass transistor. 
     
     
       39. The programmable logic block according to claim 37, wherein each of the first and the second pass transistors in each of the pair pass-transistor elements comprises a switching device having a first conduction type and a first driving capacity, and having an input terminal connected to the input terminal of the pass transistor, an output terminal connected to the output terminal of the pass transistor and a control terminal connected to the control terminal of the pass transistor;   each of the first and the second pass transistors further comprises auxiliary switching device, each having a second conduction type and a second driving capacity which is less than the first driving capacity; and   each of the auxiliary switching devices having an input terminal connected to the input terminal of the corresponding switching device, an output terminal connected to the output terminal of the corresponding switching device, and a control terminal for receiving a complementary logic signal of a logic signal received by the control terminal of the corresponding switching device.   
     
     
       40. The programmable logic block according to claim 39, wherein said control terminal of the auxiliary switching device in the second pass transistor in each of the pair pass-transistor elements is connected to the control terminal of the corresponding pair pass-transistor element; and   each of the pair pass-transistor elements further comprises an inverter having an input and an output terminal, the input terminal of the inverter is connected to the control terminal of the pair pass-transistor element, and the output terminal of the inverter is connected to the control terminal of the second pass transistor and to the control terminal of the auxiliary switching device in the first pass transistor.   
     
     
       41. The programmable logic block according to claim 39, wherein said switching devices are N channel MOS transistors having a first W/L ratio, and said auxiliary switching devices are P channel MOS transistors having a second W/L ratio which is less than the first W/L ratio. 
     
     
       42. The programmable logic block according to claim 34, wherein said multiple-input logic gate is one of a NAND, a NOR, an AND and an OR gate. 
     
     
       43. The programmable logic block according to claim 34, wherein said multiple-input logic gate is a multiple-input complementary logic gate; and   said programmable logic block further comprises a suppressor of a static feedthrough current of the multiple-input complementary logic gate.   
     
     
       44. The programmable logic block according to claim 43, wherein said suppressor of static feedthrough current comprises means for restoring potentials of all the intermediate input nodes of the multiple-input complementary logic gate in response to a potential of the output node of the multiple-input complementary logic gate. 
     
     
       45. The programmable logic block according to claim 43, wherein said multiple-input complementary logic gate is a multiple-input CMOS logic gate;   each of the pair pass-transistor elements includes two N channel MOS transistors; and   said suppressor of static feed through current comprises P channel MOS transistors each provided for each of the intermediate input nodes of the multiple-input CMOS logic gate for restoring a potential of the corresponding intermediate input node in response to a potential of the output node of the multiple-input CMOS logic gate.   
     
     
       46. The programmable logic block according to claim 34, wherein said programmable interconnections include at least two programmable switches each for programmably connecting one of the input terminals of one of the pair pass-transistor elements to one of a first and a second power supply means. 
     
     
       47. The programmable logic block according to claim 34, further comprising inverters; wherein said programmable interconnections include at least two programmable switches each for programmably connecting one of the input terminals of each of the pair pass-transistor elements to one of the signal input terminals via one of the inverters.   
     
     
       48. The programmable logic block according to claim 34, wherein said multiple-input logic gate comprises a third intermediate input node in addition to the at least two intermediate input nodes; and   said programmable interconnections include at least one programmable switch for programmably connecting said third intermediate input node to at least one of the signal input terminals.   
     
     
       49. The programmable logic block according to claim 34, wherein said programmable interconnections include at least two fixed interconnections each for connecting the output terminal of one of the pair pass-transistor elements to corresponding one of the intermediate input nodes of the multiple-input logic gates. 
     
     
       50. The programmable logic block according to claim 49, wherein said at least two pair pass-transistor elements include a third pair pass-transistor element in addition to the pair pass-transistor elements connected by the fixed interconnections; and   said programmable interconnections include at least one programmable switch for programmably connecting the output terminal of the third pair pass-transistor element to at least one of the input terminals of the pair pass-transistor elements connected by the fixed interconnections.   
     
     
       51. The programmable logic block according to claim 50, wherein said multiple-input logic gate comprises a third intermediate input node in addition to the intermediate input nodes connected by the fixed interconnections; and   said programmable interconnections further include a second programmable switch for programmably connecting the output terminal of the third pair pass-transistor logic element to the third intermediate input node of the multiple-input logic gate.   
     
     
       52. The programmable logic block according to claim 34, further comprising a second multiple-input logic gate having at least two intermediate input nodes and an output node; wherein said at least two pair pass-transistor elements comprises a first group of pair pass-transistor elements and a second group of pair pass-transistor elements each including at least two of the pair pass-transistor elements;   said programmable interconnections include a first plurality of programmable switches each for programmably connecting the output terminal of one of the pair pass-transistor elements in the second group to corresponding one of the intermediate input nodes of the second multiple-input logic gate; and   said programmable interconnections further include a second plurality of programmable switches each for programmably connecting the output terminal of one of the pair pass-transistor elements in the second group to corresponding one of the input terminals of the pair pass-transistor elements in the first group.   
     
     
       53. The programmable logic block according to claim 52, wherein said first group of the pair pass-transistor elements includes n of the pair pass-transistor elements, where n is an integer greater than one, and said second group of the pair pass-transistor elements includes 2n of the pair pass-transistor elements. 
     
     
       54. The programmable logic block according to claim 52, wherein said programmable interconnections further include at least two fixed interconnections each for connecting the output terminal of each of the pair pass-transistor elements in the first group to corresponding one of the intermediate input nodes of the multiple-input logic gate. 
     
     
       55. The programmable logic block according to claim 34, wherein said at least two pair pass-transistor elements comprises a first group of pair pass-transistor elements including two of the pair pass-transistor elements and a second group of pair pass-transistor elements including four of the pair pass-transistor elements; and   said programmable interconnections include a plurality of programmable switches each for programmably connecting the output terminal of each of the pair pass-transistor elements in the second group to corresponding one of the input terminals of the pair pass-transistor elements in the first group.   
     
     
       56. The programmable logic block according to claim 55, wherein said programmable interconnections include two fixed interconnections each for connecting the output terminal of each of the pair pass-transistor elements in the first group to corresponding one of the intermediate input node of the multiple-input logic gate. 
     
     
       57. The programmable logic block according to claim 34, wherein said multiple-input logic gate has a first driving capacity; and   each of the programmable logic blocks further comprises a driver having a second driving capacity greater than the first driving capacity.   
     
     
       58. The programmable logic block according to claim 57, wherein said multiple-input logic gate is a multiple-input CMOS logic gate and the driver is a CMOS inverter. 
     
     
       59. In a programmable logic block for use in a field programmable gate array comprising: a plurality of signal input terminals for receiving input logic signals;   at least two pair pass-transistor elements each having two input terminals, an output terminal and a control terminal;   a multiple-input logic gate having at least two intermediate input nodes and an output node; and   programmable interconnections for programmably arranging the pair pass-transistor elements and the multiple-input logic gate,   a method of programming the programmable logic block comprising the steps of: arranging the pair pass-transistor elements to form at least two pass-transistor logic trees, such that each of the pass-transistor logic trees comprises at least one of the pair pass-transistor elements and has at least two input nodes, and such that the output terminal of one of the at least one pair pass-transistor element in each of the pass-transistor logic trees acts as an intermediate output node;   connecting the at least two input nodes of each pass-transistor logic tree to corresponding ones of the signal input terminals such that, when the input logic signals are received by the plurality of signal input terminals, each of the pass-transistor logic trees receives at least two of the input logic signals and provides an intermediate logic signal through the intermediate output node to corresponding one of the intermediate input nodes of the multiple-input logic gate.     
     
     
       60. The method according to claim 59, wherein said at least two input nodes of each of the pass-transistor logic trees include the control terminal of at least one of the pair pass-transistor elements. 
     
     
       61. The method according to claim 59, wherein said step of arranging arranges the pair pass-transistor elements such that at least one of the pass-transistor logic trees comprises at least two stages. 
     
     
       62. The method according to claim 59, wherein said step of inputting includes inputting one of the input logic signals to one of the intermediate input nodes of the multiple-input logic gate to which the intermediate logic signal is not provided.