Method of fabricating gate electrodes of twin-well CMOS device

Abstract

A multi-step dry-etching method that sequentially employs plasma etching and reactive ion etching process steps to form the pairs of adjacent, doped polysilicon gate electrodes of a twin-well CMOS device. The initial dry-etching process step uses to best advantage the speed of plasma etching to rapidly form pairs of adjacent p- and n-type gate-precursor features with substantially vertical sidewalls from the upper 50-80% of a doped polysilicon layer which lies on an insulating film. The gate-precursor features and, subsequently, the gate electrodes are formed from pairs of adjacent p- and n-type regions within the doped polysilicon layer which lie over pairs of adjacent n- and p-wells (the twin wells of the CMOS device), respectively, within a substrate. The subsequent dry-etching process step uses reactive ion etching to complete the formation of the pairs of adjacent, doped polysilicon gate electrodes from the remaining 50-20% of the etched, doped polysilicon layer without over-etching the insulating film.

What is claimed is: 
     
       1. A method of fabricating on a semiconductor substrate gate electrodes of a twin-well CMOS device, the method comprising the steps of: forming within the substrate an n-well and a p-well adjacent to the n-well;   forming on the substrate an insulating film;   depositing onto the insulating film an undoped polysilicon layer, the undoped polysilicon layer having a first region over the n-well and a second region, adjacent to the first region, over the p-well;   selectively implanting p-type dopants into the first region and n-type dopants into the second region, thereby forming doped first and second polysilicon regions in the undoped polysilicon layer;   selectively and anisotropically etching, by plasma etching, upper portions of the doped first and second polysilicon regions, thereby forming first and second gate-precursor features, respectively, on the insulating film, each gate-precursor feature having substantially vertical sidewalls; and   selectively etching, by using reactive ion etching, remaining portions of the doped first and second polysilicon regions having the first and second gate-precursor features until regions of the insulating film are exposed to either side of each of the gate-precursor features, thereby fabricating the gate electrodes of the twin-well CMOS device, wherein etch gases of said reactive ion etching include HBr gas and Cl 2  gas, wherein an initial feed rate of said HBr gas is greater than an initial feed rate of said Cl 2  gas, and wherein etch rates of each of the etch gases are changed from initial feed rates to subsequent feed rates.   
     
     
       2. The method according to claim 1, wherein a mixture of etch gases used for the plasma etching consists essentially of Cl 2  gas and HBr gas. 
     
     
       3. The method according to claim 2, wherein the feed rate of HBr gas of the mixture of etch gases of the plasma etching system is at least as great as the feed rate of Cl 2  gas of the mixture of etch gases of the plasma etching system. 
     
     
       4. The method according to claim 3, wherein the feed rate of Cl 2  gas of the mixture of etch gases of the plasma etching system plus the feed rate of HBr gas of the mixture of etch gases of the plasma etching system is at least 10 sccm but is no greater than 300 sccm. 
     
     
       5. The method according to claim 1, wherein the step of selectively etching the remaining portions of the doped first and second polysilicon regions includes a sub-step of: changing the mixture of the etch gases of the reactive ion etching system from an initial mixture to a subsequent mixture.   
     
     
       6. The method according to claim 4, wherein the initial mixture of the etch gases of the reactive ion etching consists essentially of Cl 2  gas and HBr gas. 
     
     
       7. The method according to claim 6, wherein the initial feed rate of Cl 2  gas of the initial mixture of the etch gases of the reactive ion etching plus the initial feed rate of HBr rate of HBr gas of the initial mixture of the etch gases of the reactive ion etching is at least 50 sccm but is no greater than 300 sccm. 
     
     
       8. The method according to claim 4, wherein a subsequent mixture of the etch gases of the reactive ion etching consists essentially of Cl 2  gas, HBr gas, He gas, and O 2  gas. 
     
     
       9. The method according to claim 7, wherein the subsequent feed rate of Cl 2  gas of the subsequent mixture of the etch gases of the reactive ion etching plus the subsequent feed rate of HBr gas of the subsequent mixture of the etch gases of the reactive ion etching is at least 10 sccm but is no greater than 200 sccm. 
     
     
       10. The method according to claim 9, wherein the subsequent feed rate of He gas of the subsequent mixture of the etch gases of the reactive ion etching system plus the subsequent feed rate of O 2  gas of the subsequent mixture of the etch gases of the reactive ion etching system is at least 4 sccm. 
     
     
       11. The method according to claim 1, wherein a subsequent feed rate of said HBr gas is at least twice as great as a subsequent feed rate of said Cl 2  gas. 
     
     
       12. The method according to claim 1, wherein said reactive ion etching includes a cleanup phase, before introduction of said HBr gas and said Cl 2  gas, wherein native oxide formed during a transition from said plasma etching to said reactive ion etching is removed using CF 4  gas. 
     
     
       13. A method of fabricating gate electrodes of a semiconductor device, the method comprising: forming an n-well and a p-well within a substrate;   forming an insulating film on the substrate;   forming an undoped polysilicon layer on the insulating film over the n-well and p-well;   selectively implanting p-type and n-type dopants into certain portions of the undoped polysilicon layer to form first and second doped polysilicon patterns;   removing upper portions of the first and second doped polysilicon patterns using plasma etching; and   removing portions of the remaining portions of the first and second doped polysilicon patterns using reactive ion etching to fabricate the gate electrodes of the semiconductor device, wherein etch gases of said reacting ion etching include HBr gas and Cl 2  gas, wherein an initial feed rate of said HBr gas is greater than an initial feed rate of said Cl 2  gas and wherein said initial feed rates of said HBr gas and said Cl 2  are changed to subsequent feed rates, respectively.   
     
     
       14. The method according to claim 13, wherein in the first removing step, an upper 50-80% of the first and second doped polysilicon patterns is selectively etched by the plasma etching system. 
     
     
       15. The method according to claim 14, wherein in the second removing step, the remaining 50-20% of the first and second doped polysilicon patterns is selectively etched by the reactive ion etching system. 
     
     
       16. The method according to claim 15, wherein in the first removing step, Cl 2  and HBr gases are used in the plasma etching system to etch the first and second doped polysilicon patterns. 
     
     
       17. The method according to claim 13, wherein a subsequent feed rate of said HBr gas is at least twice as great as a subsequent feed rate of said Cl 2  gas. 
     
     
       18. The method according to claim 13, wherein said reactive ion etching includes a cleanup phase, before introduction of said HBr gas and said Cl 2  gas, wherein native oxide formed during a transition from said plasma etching to said reactive ion etching is removed using CF 4  gas.