Programmable logic device

Abstract

An improved programmable logic device is disclosed. In one embodiment, the programmable logic device includes a plurality of I/O cells and a plurality of logic block clusters. Each logic block cluster has a set of logic blocks and a cluster routing pool, which provides programmable connections among the logic blocks and the I/O cells. A global routing pool provides programmable connections among the logic block clusters and the I/O cells. Each logic block includes a programmable logic array with a plurality of outputs. A product term sharing array in the logic block has a plurality of bus lines, each of which is coupled to at least one of the outputs of the programmable logic array. The product term sharing array also includes a plurality of output lines, each of which is coupled to a plurality of programmable interconnections that each provide a connection to one of the bus lines. Each output line of the product term sharing array is coupled to the same number of programmable interconnections. The logic block also includes a register coupled to at least one of the output lines of the product term sharing array. The register has a data input terminal and a data output terminal. First and second output multiplexers each have a first input terminal coupled to the data input terminal of the register and a second input terminal coupled to the data output terminal of the register.

We claim: 
     
       1. A programmable logic device comprising: a programmable logic array having a plurality of outputs;   a register data multiplexer having a first input terminal coupled to a routing pool line and a second input terminal coupled to at least one of the outputs of the programmable logic array, the register data multiplexer being operable to select an input signal source from a group including the routing pool line and the at least one output of the programmable logic array, and operable to generate an output signal at an output terminal in response to the input signal source;   a register having a data input terminal coupled to the output terminal of the register data multiplexer, the register further having a data output terminal, the register being operable to receive and store the output signal of the register data multiplexer;   a first output multiplexer having a first input terminal coupled to the data input terminal of the register, the first output multiplexer having a second input terminal coupled to the data output terminal of the register; and   a second output multiplexer having a first input terminal coupled to the data input terminal of the register, the second output multiplexer having a second input terminal coupled to the data output terminal of the register;   wherein the first output multiplexer further comprises an output terminal coupled to a feedback line, the feedback line being coupled to an input terminal of the programmable logic array.   
     
     
       2. A programmable logic device comprising: a programmable logic array having a plurality of outputs;   a register data multiplexer having a first input terminal coupled to a routing pool line and a second input terminal coupled to at least one of the outputs of the programmable logic array, the register data multiplexer being operable to select an input signal source from a group including the routing pool line and the at least one output of the programmable logic array, and operable to generate an output signal at an output terminal in response to the input signal source;   a register having a data input terminal coupled to the output terminal of the register data multiplexer, the register further having a data output terminal, the register being operable to receive and store the output signal of the register data multiplexer;   a first output multiplexer having a first input terminal coupled to the data input terminal of the register, the first output multiplexer having a second input terminal coupled to the data output terminal of the register; and   a second output multiplexer having a first input terminal coupled to the data input terminal of the register, the second output multiplexer having a second input terminal coupled to the data output terminal of the register;   wherein the second output multiplexer further comprises an output terminal coupled to an output routing system.   
     
     
       3. A programmable logic device comprising: a programmable logic array having a plurality of outputs;   a register data multiplexer having a first input terminal coupled to a routing pool line and a second input terminal coupled to at least one of the outputs of the programmable logic array, the register data multiplexer being operable to select an input signal source from a group including the routing pool line and the at least one output of the programmable logic array, and operable to generate an output signal at an output terminal in response to the input signal source;   a register having a data input terminal coupled to the output terminal of the register data multiplexer, the register further having a data output terminal, the register being operable to receive and store the output signal of the register data multiplexer;   a first output multiplexer having a first input terminal coupled to the data input terminal of the register, the first output multiplexer having a second input terminal coupled to the data output terminal of the register; and   a second output multiplexer having a first input terminal coupled to the data input terminal of the register, the second output multiplexer having a second input terminal coupled to the data output terminal of the register;   wherein the first output multiplexer further comprises a select terminal coupled to a programmable cell, the first output multiplexer being operable to generate an output signal selected from a group including a data input signal of the register and a data output signal of the register, the output signal being selected in response to a select signal received from the programmable cell.   
     
     
       4. A programmable logic device comprising: a programmable logic array having a plurality of outputs;   a register data multiplexer having a first input terminal coupled to a routing pool line and a second input terminal coupled to at least one of the outputs of the programmable logic array, the register data multiplexer being operable to select an input signal source from a group including the routing pool line and the at least one output of the programmable logic array, and operable to generate an output signal at an output terminal in response to the input signal source;   a register having a data input terminal coupled to the output terminal of the register data multiplexer, the register further having a data output terminal, the register being operable to receive and store the output signal of the register data multiplexer;   a first output multiplexer having a first input terminal coupled to the data input terminal of the register, the first output multiplexer having a second input terminal coupled to the data output terminal of the register; and   a second output multiplexer having a first input terminal coupled to the data input terminal of the register, the second output multiplexer having a second input terminal coupled to the data output terminal of the register;   wherein the second output multiplexer further comprises a select terminal coupled to a programmable cell, the second output multiplexer being operable to generate an output signal selected from a group including a data input signal of the register and a data output signal of the register, the output signal being selected in response to a select signal received from the programmable cell.   
     
     
       5. A programmable logic device comprising: a plurality of I/O cells;   a plurality of logic blocks; and   a programmable routing pool operable to provide connections among the logic blocks and the I/O cells;   wherein at least one of the logic blocks includes:   a programmable logic array having a plurality of outputs;   a first logic circuit connected to received at least one of the programmable logic array outputs, the first logic circuit being operable to generate an output signal in response to at least one of the programmable logic array outputs;   a second logic circuit connected to received at least one of the programmable logic array outputs, the second logic circuit being operable to generate an output signal in response to at least one of the programmable logic array outputs;   a register data multiplexer having a first input terminal coupled to a routing pool line of the programmable routing pool, a second input terminal connected to receive the output signal of the first logic circuit and a third input terminal connected to receive the output signal of the second logic circuit, the register data multiplexer being operable to select an input signal source from a group including the routing pool line and the output signals of the first and second logic circuits, and operable to generate an output signal at an output terminal in response to the input signal source;   a register having a data input terminal coupled to the output terminal of the register data multiplexer, the register further having a data output terminal, the register being operable to receive and store the output signal of the register data multiplexer;   a first output multiplexer having a plurality of input terminals connected to a corresponding plurality of the data input terminals of the register data multiplexer, the first output multiplexer having a register data input terminal coupled to the data output terminal of the register; and   a second output multiplexer having a plurality of input terminals connected to a corresponding plurality of the data input terminals of the register data multiplexer, the second output multiplexer having a register data input terminal coupled to the data output terminal of the register.   
     
     
       6. The programmable logic device of claim 5, wherein the first output multiplexer of at least one of the logic blocks further comprises an output terminal coupled to a feedback line, the feedback line being coupled to an input terminal of the programmable logic array. 
     
     
       7. The programmable logic device of claim 5, wherein the second output multiplexer of at least one of the logic blocks further comprises an output terminal coupled to the programmable routing pool. 
     
     
       8. The programmable logic device of claim 5, wherein the first output multiplexer of at least one of the logic blocks further comprises a select terminal coupled to a programmable cell, the first output multiplexer being operable to generate an output signal selected from a group including a data input signal of the register and a data output signal of the register, the output signal being selected in response to a select signal received from the programmable cell. 
     
     
       9. The programmable logic device of claim 5, wherein the second output multiplexer of at least one of the logic blocks further comprises a select terminal coupled to a programmable cell, the first output multiplexer being operable to generate an output signal selected from a group including a data input signal of the register and a data output signal of the register, the output signal being selected in response to a select signal received from the programmable cell. 
     
     
       10. A programmable logic device comprising: a programmable logic array having a plurality of outputs;   a register coupled to at least one of the outputs of the programmable logic array, the register having a reset input and a preset input; and   a programmable switching device having an input terminal coupled to receive a reset signal, the programmable switching device having a first output terminal coupled to the reset input of the register, the programmable switching device having a second output terminal coupled to the preset input of the register, the programmable switching device being operable to programmably route the reset signal to a selected one of the reset input and the preset input of the register.   
     
     
       11. The programmable logic device of claim 10, wherein the programmable switching device comprises a demultiplexer having an input terminal operable to receive the reset signal, and having a first output terminal coupled to the reset input of the register, and having a second output terminal coupled to the preset input of the register, and having a select terminal coupled to a programmable cell, the demultiplexer being operable to route the reset signal to a selected one of the reset input and the preset input of the register in response to a select signal received from the programmable cell. 
     
     
       12. The programmable logic device of claim 10, further comprising an OR gate having a plurality of input terminals, at least one of the input terminals being coupled to one of the outputs of the programmable logic array, the OR gate further having an output terminal coupled to a data input of the register. 
     
     
       13. The programmable logic device of claim 10, further comprising an OR gate having an output terminal coupled to the reset input of the register, the OR gate having a first input terminal coupled to the programmable switching device and a second input terminal coupled to a second reset signal source, the OR gate being operable to provide a reset signal to the register in response to either one of the reset signal and a second reset signal from the second reset signal source. 
     
     
       14. The programmable logic device of claim 10, further comprising an OR gate having an output terminal coupled to the preset input of the register, the OR gate having a first input terminal coupled to the programmable switching device and a second input terminal coupled to a preset signal source, the OR gate being operable to provide a preset signal to the register in response to either one of the reset signal and a preset signal from the preset signal source. 
     
     
       15. A programmable logic device comprising: a plurality of logic blocks, each logic block having:   a programmable logic array having a plurality of outputs;   a register coupled to at least one of the outputs of the programmable logic array, the register having a reset input and a preset input; and   a programmable switching device having an input terminal coupled to receive a reset signal, the programmable switching device having a first output terminal coupled to the reset input of the register, the programmable switching device having a second output terminal coupled to the preset input of the register, the programmable switching device being operable to programmably route the reset signal to a selected one of the reset input and the preset input of the register;   a plurality of I/O cells; and   a programmable routing pool operable to provide connections among the logic blocks and the I/O cells.   
     
     
       16. The programmable logic device of claim 15, wherein the programmable switching device of at least one of the logic blocks comprises a demultiplexer having an input terminal operable to receive the reset signal, and having a first output terminal coupled to the reset input of the register, and having a second output terminal coupled to the preset input of the register, and having a select terminal coupled to a programmable cell, the demultiplexer being operable to route the reset signal to a selected one of the reset input and the preset input of the register in response to a select signal received from the programmable cell. 
     
     
       17. The programmable logic device of claim 15, wherein at least one of the logic blocks further comprises an OR gate having a plurality of input terminals, at least one of the input terminals being coupled to one of the outputs of the programmable logic array, the OR gate further having an output terminal coupled to a data input of the register. 
     
     
       18. The programmable logic device of claim 15, wherein at least one of the logic blocks further comprises an OR gate having an output terminal coupled to the reset input of the register, the OR gate having a first input terminal coupled to the programmable switching device and a second input terminal coupled to a second reset signal source, the OR gate being operable to provide a reset signal to the register in response to either one of the reset signal and a second reset signal from the second reset signal source. 
     
     
       19. The programmable logic device of claim 15, wherein at least one of the logic blocks further comprises an OR gate having an output terminal coupled to the preset input of the register, the OR gate having a first input terminal coupled to the programmable switching device and a second input terminal coupled to a preset signal source, the OR gate being operable to provide a preset signal to the register in response to either one of the reset signal and a preset signal from the preset signal source. 
     
     
       20. A method for programmably resetting a register in a logic block of a programmable logic device, comprising: receiving a reset signal at a programmable switching device in the logic block;   receiving a select signal at the programmable switching device from a programmable cell; and   providing the reset signal to a destination selected from a group including a reset input of the register and a preset input of the register by the programmable switching device in response to the select signal.   
     
     
       21. The method of claim 20, further comprising: providing an OR gate coupled to the programmable switching device and coupled to a second reset signal source; and   providing a reset signal to the reset input of the register by the OR gate in response to either one of the reset signal and a second reset signal from the second reset signal source.   
     
     
       22. The method of claim 20, further comprising: providing an OR gate coupled to the programmable switching device and coupled to a preset signal source; and   providing a preset signal to the preset input of the register by the OR gate in response to either one of the reset signal and a preset signal from the second reset signal source.   
     
     
       23. A programmable logic device comprising: a programmable logic array having a plurality of outputs;   a product term sharing array having a plurality of bus lines, each bus line being coupled to at least one of the outputs of the programmable logic array, the product term sharing array further having a plurality of output lines, each output line being coupled to a plurality of programmable interconnections, each programmable interconnection being operable to provide a connection between the output line and one of the bus lines, wherein each output line of the product term sharing array is coupled to a preselected number of programmable interconnections, the preselected number being less than the number of bus lines; and   an output processing system coupled to the output lines of the product term sharing array, the output processing system being operable to receive and process output signals from the product term sharing array.   
     
     
       24. The programmable logic device of claim 23, further comprising a plurality of OR gates, each OR gate having a plurality of input terminals, each input terminal being coupled to an output of the programmable logic array, each OR gate further having an output terminal coupled to one of the bus lines of the product term sharing array. 
     
     
       25. The programmable logic device of claim 23, further comprising a plurality of I/O cells operable to receive processed output signals from the output processing system, and operable to provide the processed output signals to a plurality of I/O pins. 
     
     
       26. The programmable logic device of claim 23, wherein the output processing system comprises: a register having a data input coupled to at least one of the output lines of the product term sharing array, the register further having a data output, the register being operable to store a data signal received on the at least one output line of the product term sharing array; and   an output multiplexer having a first input terminal coupled to a selected one of the output lines of the product term sharing array, the output multiplexer further having a second input terminal coupled to the data output of the register, the output multiplexer further having a select input terminal and an output terminal, the output multiplexer being operable to provide an output signal at the output terminal, the output signal being selected from a group including the data output of the register and the selected one of the output lines of the product term sharing array.   
     
     
       27. The programmable logic device of claim 23, wherein the programmable logic array comprises an array of AND gates. 
     
     
       28. The programmable logic device of claim 24, wherein the product term sharing array further comprises a plurality of OR gates, each OR gate having at least one input terminal coupled to at least one of the programmable interconnections, each OR gate further having an output terminal coupled to a corresponding one of the output lines of the product term sharing array. 
     
     
       29. A programmable logic device comprising: a plurality of I/O cells;   a plurality of logic blocks, each logic block having:   a programmable logic array having a plurality of outputs;   a product term sharing array having a plurality of bus lines, each bus line being coupled to at least one of the outputs of the programmable logic array, the product term sharing array further having a plurality of output lines, each output line being coupled to a plurality of programmable interconnections, each programmable interconnection being operable to provide a connection between the output line and one of the bus lines, wherein each output line of the product term sharing array is coupled to a preselected number of programmable interconnections, the preselected number being less than the number of bus lines; and   an output processing system coupled to the output lines of the product term sharing array, the output processing system being operable to receive and process output signals from the product term sharing array; and   a programmable routing pool operable to provide connections among the logic blocks and the I/O cells.   
     
     
       30. The programmable logic device of claim 29, wherein at least one of the logic blocks further comprises a plurality of OR gates, each OR gate having a plurality of input terminals, each input terminal being coupled to an output of the programmable logic array, each OR gate further having an output terminal coupled to one of the bus lines of the product term sharing array. 
     
     
       31. The programmable logic device of claim 29, wherein the I/O cells are operable to receive processed output signals from the output processing system, and operable to provide the processed output signals to a plurality of I/O pins. 
     
     
       32. The programmable logic device of claim 29, wherein the output processing system of at least one of the logic blocks comprises: a register having a data input coupled to at least one of the output lines of the product term sharing array, the register further having a data output, the register being operable to store a data signal received one the at least one output line of the product term sharing array; and   an output multiplexer having a first input terminal coupled to a selected one of the output lines of the product term sharing array, the output multiplexer further having a second input terminal coupled to the data output of the register, the output multiplexer further having a select input terminal and an output terminal, the output multiplexer being operable to provide an output signal at the output terminal, the output signal being selected from a group including the data output of the register and the selected one of the output lines of the product term sharing array.   
     
     
       33. The programmable logic device of claim 29, wherein the programmable logic array of at least one of the logic blocks comprises an array of AND gates. 
     
     
       34. The programmable logic device of claim 29, wherein the product term sharing array of at least one of the logic blocks further comprises a plurality of OR gates, each OR gate having at least one input terminal coupled to at least one of the programmable interconnections, each OR gate further having an output terminal coupled to a corresponding one of the output lines of the product term sharing array. 
     
     
       35. A programmable logic device comprising: a programmable logic array having a universal output and a plurality of individual outputs;   a plurality of registers, each register having a data input, a data output and a clock input, the data input of at least one of the registers being coupled to at least one of the individual outputs of the programmable logic array, the clock input of each register being coupled to the universal output of the programmable logic array; and   a routing pool coupled to the data output of each register, the routing pool being operable to programmably route data output signals from the registers.   
     
     
       36. A programmable logic device comprising: a plurality of logic blocks, each logic block having:   a programmable logic array having a universal output and a plurality of individual outputs; and   a plurality of registers, each register having a data input, a data output and a clock input, the data input of at least one of the registers being coupled to at least one of the individual outputs of the programmable logic array, the clock input of each register being coupled to the universal output of the programmable logic array;   a plurality of I/O cells; and   a programmable routing pool coupled to the data outputs of the registers and operable to provide connections among the logic blocks and the I/O cells.   
     
     
       37. A programmable logic device comprising: a plurality of I/O cells;   a plurality of logic block clusters, each logic block cluster having a plurality of logic blocks and a cluster routing pool operable to provide programmable connections among the logic blocks and selected ones of the I/O cells, each logic block having:   a programmable logic array having a plurality of outputs;   a product term sharing array having a plurality of bus lines, each bus line being coupled to at least one of the outputs of the programmable logic array, the product term sharing array further having a plurality of output lines, each output line being coupled to a plurality of programmable interconnections, each programmable interconnection being operable to provide a connection to one of the bus lines, wherein each output line of the product term sharing array is coupled to the same number of programmable interconnections;   a register coupled to at least one of the output lines of the product term sharing array, the register having a data input terminal and a data output terminal;   a first output multiplexer having a first input terminal coupled to the data input terminal of the register, the first output multiplexer having a second input terminal coupled to the data output terminal of the register; and   a second output multiplexer having a first input terminal coupled to the data input terminal of the register, the second output multiplexer having a second input terminal coupled to the data output terminal of the register; and   a global routing pool operable to provide programmable connections among the logic block clusters and the I/O cells.   
     
     
       38. A programmable logic device, comprising: a programmable logic array, said programmable logic array providing a plurality of logic signals at a plurality of output terminals positioned generally along the extent of a line segment; and   a programmable signal steering circuit having a plurality of output terminals, coupled to receive said logic signals from said plurality of output terminals of said programmable logic array, said programmable interconnect circuit allowing each of said logic signals to be coupled to an equal number of said output terminals of said programmable interconnect circuit.   
     
     
       39. A programmable logic device as in claim 38, wherein said programmable logic array comprises an AND array. 
     
     
       40. A programmable logic device as in claim 39, wherein said AND array providing a plurality of product term signals, said programmable logic array further comprises a plurality of OR logic gates, each of said OR logic gates receiving a predetermined number of said product term signals and providing as output one of said output signals of said programmable logic array. 
     
     
       41. A programmable logic device as in claim 38, wherein said programmable logic array further comprises a second set of output terminals each receiving said logic signals, each of said second set of output terminals being coupled to a clock terminal of a state element. 
     
     
       42. A programmable logic device as in claim 38, wherein said programmable logic array further comprises a second set of output terminals each receiving said logic signals, each of said second set of output terminals being coupled to a reset terminal of a state element. 
     
     
       43. A programmable logic device as in claim 38, wherein said programmable logic array further comprises a second set of output terminals each receiving said logic signals, each of said second set of output terminals being coupled to a preset terminal of a state element. 
     
     
       44. A programmable logic device as in claim 38, wherein said programmable logic array further comprises a second set of output terminals each receiving said logic signals, each of said second set of output terminals being coupled to a control terminal of an output buffer. 
     
     
       45. A programmable logic device as in claim 38 wherein said programmable signal steering circuit couples each logic signal to a group of output terminals of said programmable signal steering circuit bearing a predetermined positional relationship to each other, except at a selected group of output terminals of said programmable signal steering array at opposite ends of said line segment; said programmable signal steering circuit couples logic signals to said output terminals of said selected group as if output terminals in said selected group bears said predetermined positional relationship each other. 
     
     
       46. A programmable logic device, comprising: a programmable logic array providing as output a plurality of logic signals; and   first and second programmable logic circuits each including a terminal for receiving a common control signal and a plurality of elements each having a control input terminal, each programmable logic circuit being programmable to select for each of said control input terminal either one of said logic signals or said common control signal.   
     
     
       47. A programmable logic device as in claim 46, wherein said control input terminal receives a clock signal. 
     
     
       48. A programmable logic device as in claim 47, wherein said control input terminal receives a reset signal. 
     
     
       49. A programmable logic device as in claim 46, wherein said control input terminal receives a output enable signal. 
     
     
       50. A programmable logic device as in claim 47, wherein said control input terminal receives a preset signal. 
     
     
       51. A programmable logic device comprising: a programmable logic array having a plurality of outputs;   a first logic circuit connected to received at least one of the programmable logic array outputs, the first logic circuit being operable to generate an output signal in response to at least one of the programmable logic array outputs;   a second logic circuit connected to received at least one of the programmable logic array outputs, the second logic circuit being operable to generate an output signal in response to at least one of the programmable logic array outputs;   a register data multiplexer having a first input terminal connected to receive the output signal of the first logic circuit and a second input terminal connected to receive the output signal of the second logic circuit, the register data multiplexer being operable to select an input signal source from a group including the output signals of the first and second logic circuits, and operable to generate an output signal at an output terminal in response to the input signal source;   a register having a data input terminal coupled to the output terminal of the register data multiplexer, the register further having a data output terminal, the register being operable to receive and store the output signal of the register data multiplexer;   a first output multiplexer having a first input terminal connected to receive the output signal of the first logic circuit, the first output multiplexer having a second input terminal connected to receive the output signal of the second logic circuit, the first output multiplexer having a third input terminal coupled to the data output terminal of the register; and   a second output multiplexer having a first input terminal connected to receive the output signal of the first logic circuit, the second output multiplexer having a second input terminal connected to receive the output signal of the second logic circuit, the second output multiplexer having a third input terminal coupled to the data output terminal of the register.