Logic element for a programmable logic integrated circuit

Abstract

A logic element (300) for a programmable logic device. The logic element (300) allows two independent logic functions to be carried out during the same clock cycle. A 4-input look-up table (406) is provided using a 3-input look-up table (434) and two 2-input look-up tables. The results of the 4-input lookup table (406) and the 3-input lookup table (434) may be routed simultaneously from the logic element. It also allows a signal to be routed through a logic element (300) while carrying out an independent logic function. Carry logic (425) is provided. The results of the carry logic (486) may be routed to the global and local interconnect structure of the programmable logic device.

What is claimed is: 
     
       1. A logic element comprising: a first lookup table having a first plurality of inputs, the first lookup table implementing a first logic function;   a second lookup table having a second plurality of inputs, the second lookup table implementing a second logic function;   control circuitry coupled to the first lookup table and the second lookup table, the control circuitry configured to selectively combine the first lookup table and the second lookup table to implement a third logic function; and   a first output terminal, wherein the first output terminal selectively outputs the result of the first logic function, the result of the third logic function or the signal carried on one of the first and second plurality of inputs.   
     
     
       2. The logic element of claim 1 further comprising a second output terminal, wherein the second output terminal selectively outputs the results of the third logic function. 
     
     
       3. The logic element of claim 1 wherein the first plurality of inputs is the same as the second plurality of inputs. 
     
     
       4. The logic element of claim 1 wherein the control circuitry includes a multiplexer with a first input coupled to the first lookup table and a second input coupled to the second lookup table. 
     
     
       5. The logic element of claim 1 further comprising a storage device to store a result of the third logic function. 
     
     
       6. The logic element of claim 1 wherein the second lookup table includes a plurality of lookup tables. 
     
     
       7. The logic element of claim 6 wherein the first lookup table is 3-input look-up table, and the second lookup table is a 3-input look-up table comprised of two 2-input lookup tables. 
     
     
       8. The logic element of claim 1 further comprising a first multiplexer coupled to the first output terminal, the first multiplexer having a first input coupled to the first lookup table and a second input coupled to the output of the control circuitry, wherein the result of the first logic function and the result of the third logic function may be selectively provided to the first output terminal. 
     
     
       9. The logic element of claim 8 further comprising a second multiplexer coupled to a second output terminal, the second multiplexer having a first input coupled to the control circuitry wherein the result of the third logic function may be selectively provided to the second output terminal. 
     
     
       10. The logic element of claim 9 further comprising: a third input for controlling the control circuitry; and   a third input for the first multiplexer, the third input being coupled to a given one of the first and second plurality of inputs, whereby a signal on the given one of the first and second plurality of inputs may be selectively provided to the first output terminal.   
     
     
       11. The logic element of claim 1 wherein the first logic function is independent of the second logic function. 
     
     
       12. A programmable logic device with a logic element as recited in claim 1. 
     
     
       13. A digital system comprising a programmable logic device with a logic element as recited in claim 1. 
     
     
       14. A logic element comprising: a first lookup table having a first plurality of inputs the first lookup table implementing a first logic function;   a second lookup table having a second plurality of inputs the second lookup table implementing a second logic function;   control circuitry coupled to the first lookup table and the second lookup table the control circuitry configured to selectively combine the first lookup table and the second lookup table to implement a third logic function;   a first output terminal;   a second output terminal;   a first multiplexer coupled to the first output terminal, the first multiplexer having a first input coupled to the first lookup table and a second input coupled to the output of the control circuitry wherein the result of the first logic function and the result of the third logic function may be selectively provided to the first output terminal;   a second multiplexer coupled to the second output terminal, the second multiplexer having a first input coupled to the control circuitry wherein the result of the third logic function may be selectively provided to the second output terminal; and   a storage element for storing the result of the third logic function, the output of the storage element being coupled to the second input of the first multiplexer and the first input of the second multiplexer.   
     
     
       15. A logic element for a programmable logic device, the programmable logic device having an interconnect structure for coupling a plurality of logic elements together, the logic element comprising: a plurality of input terminals;   a logic function block coupled to the input terminals and providing a logic result;   carry logic for determining a carry result from the logic function block;   an output terminal for coupling to the interconnect structure of the programmable logic device; and   control circuitry for selectively passing the carry result, the logic result, or a signal on one of the plurality of input terminals to the output terminal.   
     
     
       16. A logic element for a programmable logic device, the programmable logic device having an interconnect structure for coupling a plurality of logic elements together, the logic element comprising: a plurality of input terminals;   a logic function block coupled to the input terminals and providing a logic result;   an output terminal for coupling to the interconnect structure of the programmable logic device; and   control circuitry for selectively passing a signal on one of the plurality of input terminals to the output terminal and selectively passing the logic result to the output terminal.   
     
     
       17. A programmable logic integrated circuit comprising: a plurality of logic array blocks, the logic array blocks being interconnected by a global interconnect structure and having a plurality of logic elements, the logic elements being interconnected by a local interconnect structure, the logic element comprising: a plurality of input terminals;   a first lookup table coupled to at least one of the input terminals for implementing a first logic function; a second logic function block coupled to at least one of the input terminals for implementing a second logic function;   control circuitry coupled to the first lookup table and the second lookup table, the control circuitry configured to selectively combine the first lookup table and the second lookup table to implement a third logic function; and   carry logic for determining a carry result from the second logic function block;     a first multiplexer, a first input of the first multiplexer being coupled to the first lookup table, a second input of the first multiplexer being coupled to the control circuitry device for selectively passing the stored result of the third logic function, a third input of the first multiplexer being coupled to the carry logic for selectively passing the carry result, and a fourth input to the first multiplexer being coupled to particular one of the plurality of input terminals for selectively passing a signal on the particular one of the plurality of input terminals;   a second multiplexer, a first input of the second multiplexer being coupled to the first lookup table for selectively passing the result of the first logic function, a second input of the second multiplexer being coupled to the control circuitry for selectively passing the result of the third logic function, and a third input of the second multiplexer being coupled to the carry logic for selectively passing the carry result;   a first output terminal for coupling the output the first multiplexer to the global interconnect structure; and   a second output terminal for coupling the output of the second multiplexer to the local interconnect structure.   
     
     
       18. The programmable logic integrated circuit of claim 17 further comprising a storage device for storing the result of the third logic function, an output of the storage device being coupled to the second input of the first and second multiplexers. 
     
     
       19. A programmable logic integrated circuit, comprising: an interconnect structure;   a plurality of logic elements, the logic elements comprising: a first lookup table having a first plurality of inputs, the first lookup table implementing a first logic function;   a second lookup table having a second plurality of inputs, the second lookup table implementing a second logic function, and   control circuitry coupled to the first lookup table and the second lookup table, the control circuitry configured to selectively combine the first lookup table and the second lookup table to implement a third logic function; and   a first output coupled to the interconnect structure, wherein the first output terminal selectively outputs the result of the first lookup table, the result of the third logic function, or a signal on one of the first and second plurality of inputs.     
     
     
       20. A logic element comprising: a first lookup table having a first plurality of inputs, the first lookup table implementing a first logic function;   a second lookup table having a second plurality of inputs, the second lookup table implementing a second logic function;   control circuitry coupled to the first lookup table and the second lookup table, the control circuitry configured to selectively combine the first lookup table and the second lookup table to implement a third logic function;   carry logic for determining a carry result from the second logic function block;   a first output terminal;   a second output terminal;   a first multiplexer coupled to the first output terminal, the first multiplexer having a first input coupled to the first lookup table, a second input coupled to an output of the control circuitry, and a third input coupled to the carry logic, wherein the result of the first logic function, the result of the third logic function, and the carry result may be selectively provided to the first output terminal; and   a second multiplexer coupled to the second output terminal, the second multiplexer having a first input coupled to the control circuitry and a second input coupled to the carry logic, wherein the result of the third logic function and the carry result may be selectively provided to the second output terminal.