Servo demodulator and method for synchronous servo demodulation

Abstract

A servo demodulator (20) is provided for generating a track identification signal (148) and a position error signal (150) from a servo wedge signal, such as a filtered servo wedge signal (112), in response to the processing of the servo wedge signal by a read channel (18). The servo demodulator (20) includes a servo clock generation circuit (90), a position error signal circuit (92), and a track identification circuit (76). The servo clock generation circuit (90) generates a synchronous servo clock signal (102) in response to receiving a servo reference clock signal (110) and the filtered servo wedge signal (112). The synchronous servo clock signal (102) is provided to the read channel (18) for use in processing the servo wedge signal. The position error signal circuit (92) generates the position error signal (150) in response to receiving the synchronous servo clock signal (102) from the servo clock generation circuit (90) and a synchronously sampled servo wedge signal (114) from the read channel (18). The read channel (18) generates the synchronously sampled servo wedge signal (114) by using the synchronous servo clock signal (102) to synchronously sample the servo wedge signal. The track identification circuit (76) generates the track identification signal (148) in response to receiving a digital servo wedge signal (116) from the read channel (18).

What is claimed is: 
     
       1. A servo demodulator for generating a track identification signal and a position error signal in response to the processing and generation of a digital servo wedge signal by a synchronously sampled read channel, the servo demodulator comprising: a servo clock generation circuit operable to generate a synchronous servo clock signal in response to receiving a reference clock signal and the servo wedge signal, the servo clock signal provided to the read channel for processing of the servo wedge signal;   a position error signal circuit operable to generate a position error signal in response to receiving the synchronous servo clock signal of the servo clock generation circuit and a synchronously sampled servo wedge signal from the read channel; and   a track identification circuit operable to generate a track identification signal in response to receiving a digital servo wedge signal from the read channel.   
     
     
       2. The servo demodulator of claim 1, wherein the synchronously sampled servo wedge signal is generated in the read channel by synchronously sampling the servo wedge signal using the synchronous servo clock signal. 
     
     
       3. The servo demodulator of claim 2, wherein the digital servo wedge signal is generated in the read channel by synchronously sampling the servo wedge signal using the synchronous servo clock signal and performing maximum likelihood detection on the synchronously sampled servo wedge signal. 
     
     
       4. The servo demodulator of claim 2, wherein the servo wedge signal includes an address mark portion, a track identification portion, and a position error portion. 
     
     
       5. The servo demodulator of claim 4, wherein the position error signal circuit includes an address mark circuit operable to receive and process the synchronously sampled servo wedge signal and to enable an address mark enable signal indicating that the address mark portion of the servo wedge signal has been provided. 
     
     
       6. The servo demodulator of claim 2, wherein the servo wedge signal includes a position error portion and the position error portion includes a plurality of position error bursts, and the position error circuit is operable to generate the position error signal when the synchronously sampled servo wedge signal provides the position error portion. 
     
     
       7. The servo demodulator of claim 1, wherein the servo clock generation circuit comprises: a zero phase restart circuit operable to receive the reference clock signal and the servo wedge signal and to generate a zero phase restart signal having a duration equivalent to the phase difference between the reference clock signal and the servo wedge signal; and   a delay lock loop circuit operable to receive the reference clock signal and the zero phase restart signal and to generate the synchronous servo clock signal by delaying the reference an amount equivalent to the zero phase restart signal.   
     
     
       8. The servo demodulator of claim 1, wherein the servo wedge signal includes a header portion and the servo clock generation circuit generates the synchronous servo clock signal when the servo wedge signal provides the header portion. 
     
     
       9. The servo demodulator of claim 1, wherein the track identification circuit is a shift register operable to receive the digital servo wedge signal during a period of time when the digital servo wedge signal provides track identification information. 
     
     
       10. A servo demodulator for generating a track identification signal and a position error signal in response to processing generation of a digital servo wedge signal by a synchronously sampled read channel, the servo demodulator comprising: a servo clock generation circuit operable to generate a synchronous servo clock signal in response to receiving a reference clock signal and the servo wedge signal, the servo clock signal provided to the read channel for processing of the servo wedge signal;   a position error signal circuit operable to generate a position error signal in response to receiving the synchronous servo clock signal of the servo clock generation circuit and a synchronously sampled servo wedge signal from the read channel; and   a track identification circuit operable to generate a track identification signal in response to receiving a digital servo wedge signal from the read channel,   wherein the synchronously sampled servo wedge signal is generated in the read channel by synchronously sampling the servo wedge signal using the synchronous servo clock signal,   wherein the servo wedge signal includes a position error portion and the position error portion includes a plurality of position error bursts, and the position error circuit is operable to generate the position error signal when the synchronously sampled servo wedge signal provides the position error portion, and   wherein the position error signal circuit comprises: a plurality of converting circuits for receiving and processing the plurality of position error bursts provided by the synchronously sampled servo wedge signal to generate the position error signal; and   a state machine operable to receive the synchronous servo clock signal and to provide a plurality of enabling signals to enable each of the plurality of converting circuits to process a corresponding one of the plurality of position error bursts.     
     
     
       11. The servo demodulator of claim 10, wherein each one of the position error bursts, provided by the synchronously sampled servo wedge signal, include a number of samples, and wherein each one of the plurality of converting circuits comprise: a summing circuit operable to sum the number of samples from one of the position error bursts and to generate an output in response; and   an analog-to-digital converter operable to receive the output from the summing circuit and to generate a digital output signal that serves as the position error signal in response.   
     
     
       12. The servo demodulator of claim 10, wherein each one of the position error bursts, provided by the synchronously sampled servo wedge signal, include a number of samples, and wherein each one of the plurality of converting circuits comprise: an analog-to-digital converter operable to receive the position error bursts in the analog domain and to convert the position error bursts to the digital domain; and   a summing circuit operable to receive the number of samples from one of the position error bursts in the analog domain and to sum the number of samples to generate the position error signal.   
     
     
       13. A servo demodulator for generating a track identification signal and a position error signal in response to processing and generation of a digital servo wedge signal by a synchronously sampled read channel, the servo demodulator comprising: a servo clock generation circuit operable to generate a synchronous servo clock signal in response to receiving a reference clock signal and the servo wedge signal, the servo clock signal provided to the read channel for processing of the servo wedge signal;   a position error signal circuit operable to generate a position error signal in response to receiving the synchronous servo clock signal of the servo clock generation circuit and a synchronously sampled servo wedge signal from the read channel; and   a track identification circuit operable to generate a track identification signal in response to receiving a digital servo wedge signal from the read channel,   wherein the synchronously sampled servo wedge signal is generated in the read channel by synchronously sampling the servo wedge signal using the synchronous servo clock signal,   wherein the servo wedge signal includes an address mark portion, a track identification portion, and a position error portion, and   wherein the position error signal circuit is further operable to generate a track enable signal indicating when the track identification portion of the servo wedge signal is being provided, and the track identification circuit is operable to generate a track identification signal in response to receiving the track enable signal and the digital servo wedge signal.   
     
     
       14. A servo demodulator for generating a track identification signal and a position error signal in response to processing and generation of a digital servo wedge signal by a synchronously sampled read channel, the servo demodulator comprising: a servo clock generation circuit operable to generate a synchronous servo clock signal in response to receiving a reference clock signal and the servo wedge signal, the servo clock signal provided to the read channel for processing of the servo wedge signal;   a position error signal circuit operable to generate a position error signal in response to receiving the synchronous servo clock signal of the servo clock generation circuit and a synchronously sampled servo wedge signal from the read channel; and   a track identification circuit operable to generate a track identification signal in response to receiving a digital servo wedge signal from the read channel,   wherein the synchronously sampled servo wedge signal is generated in the read channel by synchronously sampling the servo wedge signal using the synchronous servo clock signal,   wherein the servo wedge signal includes an address mark portion, a track identification portion, and a position error portion,   wherein the position error signal circuit includes an address mark circuit operable to receive and process the synchronously sampled servo wedge signal and to enable an address mark enable signal indicating that the address mark portion of the servo wedge signal has been provided, and   wherein the address mark circuit comprises: a rectifier circuit operable to rectify the synchronously sampled servo wedge signal and to generate a rectified synchronously sampled servo wedge signal in response;   a comparator operable to compare the rectified synchronously sampled servo wedge signal and a threshold signal and to generate a comparison signal in response, the comparison signal indicating whether the rectified synchronously sampled servo wedge signal is larger than the threshold signal; and   a timer operable to receive the comparison signal and to enable an address mark enable signal after receiving the comparison signal in a known state for a period of time.     
     
     
       15. The servo demodulator of claim 14, wherein the timer is a down counter that generates the address mark enable in an enabled state after receiving a number of consecutive comparison signal values indicating that the threshold signal is larger than the rectified synchronously sampled servo wedge signal. 
     
     
       16. A servo system for generating a track identification signal and a position error signal from a servo wedge signal, the servo system comprising: a synchronously sampled read channel operable to receive the servo wedge signal and to generate a filtered servo wedge signal, the read channel further operable to receive a synchronous servo clock signal and the servo wedge signal and to generate a synchronously sampled servo wedge signal and a digital servo wedge signal in response;   a servo clock generation circuit operable to generate the synchronous servo clock signal in response to receiving a reference clock signal and the filtered servo wedge signal from the read channel;   a position error signal circuit operable to generate a position error signal in response to receiving the synchronous servo clock signal from the servo clock generation circuit and the synchronously sampled servo wedge signal from the read channel; and   a track identification circuit operable to generate a track identification signal in response to receiving the digital servo wedge signal from the read channel.   
     
     
       17. The servo system of claim 16 wherein the synchronously sampled read channel is a partial response, maximum likelihood read channel using the synchronous servo clock signal to sample the servo wedge signal. 
     
     
       18. A method for synchronous servo demodulation of a servo wedge signal containing position error signal information and track identification information, the method comprising the steps of: receiving a filtered servo wedge signal and a reference clock signal;   generating a synchronous servo clock signal in response;   providing the synchronous servo clock signal and the servo wedge signal to a read channel;   generating a synchronously sampled servo wedge signal and a digital servo wedge signal in the read channel;   receiving the synchronous servo clock signal and the synchronously sampled servo wedge signal;   generating a position error signal in response to said synchronous servo clock signal and the synchronously sampled servo wedge signal;   receiving the digital servo wedge signal; and   generating a track identification signal in response to said digital servo wedge signal.   
     
     
       19. The method of claim 18, further comprising the step of generating an address mark enable signal in an enabled state indicating that track identification information will be provided through the digital servo wedge signal. 
     
     
       20. The method of claim 19, wherein the servo wedge signal includes an address mark portion, a track identification portion, and a position error portion.