Cyclic code phase multiple access for inbound satellite communications

Abstract

A satellite communication system comprising of a central hub/gateway station and remote very small aperture terminal (VSAT) stations. VSAT inbound transmissions are spread in bandwidth using an assigned PN code sequence. This sequence is derived as a cyclic function of a base sequence for use by the group of VSATs. The gateway transmits a continuous outbound signal that functions as the network frequency and timing reference. In addition, the gateway periodically forms timing and frequency error estimates on each VSAT transmission and broadcasts these results over the outbound channel to the VSATs. Use of the outbound reference coupled with these time and frequency measurements enable all VSAT inbound transmissions within a group to be bit synchronized. Bit level synchronization enable the system to gain the full advantage of the correlation properties of the cyclic codes to improve multiple access performance as compared to asynchronous or chip synchronous code division multiple access (CDMA) techniques. N active users can be supported with an N length code in this system even for small values of N (N≦15). The synchronized, cyclic relationship of the inbound transmissions enables the gateway to receive and demodulate a group of channels using a single receiver. The gateway station includes a correlator receiver which is synchronized with the gateways outbound network reference and which contains all the cyclic PN code sequences to detect correlations between the pseudo-randomly modulated data bits corresponding to the cyclic PN sequence bits of the VSAT stations.

What is claimed is: 
     
       1. In a satellite communications system, a synchronous satellite terminal (ST) for receiving outbound communication signals from a hub and for transmitting inbound communication signals to the hub, the ST comprising: a chip rate clock generator that recovers a bit timing clock signal received by the satellite terminal and generates a chip rate clock signal;   a pseudo-noise (PN) code generator that receives the chip rate clock signal and a bit rate clock signal, and generates a cyclic shift inphase (I) PN code sequence and a cyclic shift quadrature (Q) PN code sequence;   a differential encoder that differentially encodes data;   a spreader that utilizes the I and Q PN code sequences to spread the encoded data; and   a phase-shift keying modulator that receives the spread data and modulates a carrier with the spread data for transmission to the hub.   
     
     
       2. The ST defined in claim 1, wherein the Q PN code sequence is the reciprocal of the I PN code sequence. 
     
     
       3. The ST defined in claim 1, wherein the PN code generator is initialized by a channel assignment signal from the hub. 
     
     
       4. The ST defined in claim 1, wherein a control channel signal received from the hub provides timing adjustment information to adjust the phase of the chip rate clock. 
     
     
       5. The ST defined in claim 1, wherein the encoded data is demultiplexed into an inphase stream and a quadrature stream. 
     
     
       6. The ST defined in claim 5, wherein the spreader performs an exclusive-or (XOR) operation on the I PN code sequence and the inphase stream, and performs an XOR operation on the Q PN code sequence and the quadrature stream so as to form a spread Q stream. 
     
     
       7. The ST defined in claim 6, wherein the spread Q stream is delayed by a fraction of a chip period. 
     
     
       8. A satellite communications system, including a cyclic correlator for receiving an inbound communication signal from a plurality of satellite terminals, the inbound communication signal comprising a serial stream of spread spectrum symbols comprising: a delay line comprising 2N-1 storage elements, wherein N is a length in chips of a maximal length sequence code utilized for despreading the received symbols from the inbound communication signal;   a set of 2N-1 multipliers receiving data from the delay line elements, wherein each delay line element feeds a corresponding multiplier, and wherein each multiplier has a tap and the taps of the multipliers are respectively set to different values (+1 and -1) corresponding to a cyclic pattern with which the symbols of the received communication signals from the satellite terminals have been spread; and   an adder for summing the outputs of the multipliers thereby providing a set of data samples associated with symbols communicated from one of the satellite terminals.   
     
     
       9. The system defined in claim 8, wherein the cyclic correlator is utilized in a correlator module to despread the received communication signal in a baseband channel, the module comprising: a chip samples store and insert zeros module that buffers input baseband samples of the received communication signal and inserts a selected number of zeros prior to processing by the cyclic correlator processor;   a chip delay module for receiving the channel's despread data samples from the cyclic correlator processor, wherein each communicated symbol is divided into two equal length sections, and delaying each data sample by N chips to time align the two sections of the symbol; and   an adder that sums the time aligned sections of the symbol.   
     
     
       10. The system defined in claim 9, wherein the sections of each symbol are added, if the channel is an inphase channel, and one of the sections is subtracted from the other section of each symbol, if the channel is a quadrature channel. 
     
     
       11. The system defined in claim 9, wherein the correlator module is one of a plurality of correlator modules comprising a portion of a synchronous baseband correlator circuit for despreading an inphase pseudo-noise (PN) code and a quadrature PN code in a set of inphase and quadrature baseband channels that comprise the received communication signal, the baseband correlator additionally comprising: at least one analog-to-digital converter for the inphase channel and the quadrature channel, the converter generating a plurality of samples per chip so as to produce inphase and quadrature digitized signals;   a chip matched filter (CMF) to improve a composite signal-to-noise ratio for each of the inphase and quadrature digitized signals; and   a set of downsamplers to decimate the filtered signals down to a chip rate, wherein the quadrature channel is modulated with a one-half chip duration staggering relative to the inphase channel and the staggering is accounted for by clocking the quadrature code samples with an inverted chip rate clock, and wherein the output of each downsampler is fed to an associated one of the correlator modules.   
     
     
       12. A satellite communications system, comprising: a hub; and   a plurality of satellite terminals (STs), wherein each ST communicates with the hub using a bit synchronous, spread spectrum multiple access protocol, each ST assigned a unique code sequence cyclically related to the other code sequences, wherein the system utilizes a maximal length sequence (MLS) code of length N chips, and wherein a cyclic correlation function for the length N code results in N for a zero cyclic shift and -1 for each of the remaining N-1 shifts.   
     
     
       13. A satellite communications system, comprising: a hub comprising a cyclic correlation receiver, the correlation receiver including a linear correlator of length 2N-1 chips; and   a plurality of satellite terminals (STs), wherein each ST communicates with the hub using a bit synchronous, spread spectrum multiple access protocol, each ST assigned a unique code sequence cyclically related to the other code sequences, wherein the system utilizes a maximal length sequence (MLS) code of length N chips.