Slew rate control circuit

Abstract

A noise limited, video, digital to analog converter having an output transition time control with multiple discrete transition times. This is accomplished by a DAC control circuit in which the slew rate of the current is controlled by providing set current levels in the inverters that drive the DAC output current switches thus limiting the current available for charging and discharging the capacitance on the nodes which control the output signal. Additional control is provided by voltage clamping of these nodes which reduces the input voltage to the analog output and results in a cleaner output waveform. By so regulating and controlling the charging and discharging of these nodes, the variations in operation of the circuit due to the process used to produce the circuit in integrated form as well as temperature and supply voltage are further substantially reduced.

What is claimed is: 
     
       1. A slew rate control circuit comprising: a pair of inverter circuits;   each of said inverter circuits comprising first and second transistors and being coupled between current limiting transistors;   an output current switch comprising a pair of switching transistors, each of said switching transistors being coupled through a respective node to a respective one of said inverter circuits; and   means, including a current regulator circuit, for providing a set of current levels in the inverter circuits to define the current available for charging and discharging the capacitance on each respective node.   
     
     
       2. The circuit of claim 1 wherein there is further provided: voltage clamping means coupled to said nodes to reduce the input voltage required to activate said current switch and provide a cleaner waveform at the output of said current switch.   
     
     
       3. The circuit of claim 1 wherein said means for providing set current levels further includes a regulator circuit comprising: first, second, and third current conducting legs;   first and second voltage outputs;   said first leg including a first current conducting transistor and a switching transistor, said transistors being of a first conductivity type and in series between said first voltage source and said first voltage output;   said first leg further including a first current limiting transistor of a second conductivity type coupled between said first voltage output and a second voltage source;   said second leg including a second current conducting transistor of said first conductivity type coupled to said first voltage output; and   said third leg including a third current conducting transistor of said first conductivity type coupled between said first voltage source and said second voltage output, and further including a second current limiting transistor of said second conductivity type coupled between said second voltage output and said second voltage source;   said first voltage output being coupled to control the first current source transistor; and   said second voltage output being coupled to control the second current source transistor.   
     
     
       4. A circuit comprising: a pair of inverters, each having inputs thereto;   each of said inverter circuits being coupled to a respective current limiting transistor;   a control circuit means for controlling the slew rate of the current, the circuit further including a current switch which can be coupled via respective nodes to a pair of inverter inputs;   means including said current limiting transistor for providing set current levels in each inverter coupled to the output current switch to limit the current available for charging and discharging the capacitance on the nodes so as to control the output signal provided by said current switch; and   a voltage clamping transistor coupled to each of said nodes to reduce the input voltage to the nodes so as to produce a cleaner output waveform.   
     
     
       5. The circuit of claim 4 wherein said means for providing set current levels comprises: a first and a second current source transistor of a first conductivity type respectively coupled between and in series with each respective inverter circuit and a first voltage source; and   a third and a fourth current source transistor of a second conductivity type respectively coupled between and in series with each respective inverter circuit and a second voltage source.   
     
     
       6. The circuit of claim 5 wherein said means further includes a regulator circuit comprising: first, second, and third conducting legs; and   first and second voltage outputs;   said first leg including a first current conducting transistor and a switching transistor, said transistors being of a first conductivity type and in series between a first voltage source and said first voltage output, and further including a first current limiting transistor of a second conductivity type coupled between said first voltage output and a second voltage source;   said second leg including a second current conducting transistor of said first conductivity type coupled to said first voltage output; and   said third leg including a third current conducting transistor of said first conductivity type coupled between said first voltage source and said second voltage output, and further including a second current limiting transistor of said second conductivity type coupled between said second voltage output and said second voltage source;   said first voltage output being coupled to control the first and second current source transistors; and   said second voltage output being coupled to control the third and fourth current source transistors.   
     
     
       7. The circuit of claim 6 wherein said first and second current source transistors are P-type field effect transistors and have their gates coupled to said first voltage output and said third and fourth current source transistors are N-type field effect transistors and have their gates coupled to said second voltage output. 
     
     
       8. The circuit of claim 7 wherein there is further provided means for switching said switching transistor from a conductive to a nonconductive state to control the amount of current applied to said first output. 
     
     
       9. The circuit of claim 8 wherein there is further provided means for turning off said first and second current limiting transistors of said second conductivity type and for turning off the third current conducting transistor of said first conductivity type in said third leg. 
     
     
       10. The circuit of claim 7 wherein the first current conducting transistor of said first leg and said second current conducting transistor of said second leg each have their control electrode coupled to a regulated voltage source. 
     
     
       11. The circuit of claim 9 wherein said transistors are field effect transistors. 
     
     
       12. the circuit of claim 9 wherein said transistors are bipolar transistors. 
     
     
       13. A slew rate control circuit comprising: a pair of inverter circuits;   said inverter circuits being coupled through a current limiting transistor to a voltage source;   an output current switch comprising a pair of switching transistors, each of said switching transistors being coupled through a respective node to a respective one of said inverter circuits; and   means for providing a plurality of sets of current levels in the inverter circuits to limit the current available for charging and discharging the capacitance on each respective node.   
     
     
       14. A regulator circuit comprising: first, second, and third current conducting legs;   first and second voltage sources; and   first and second voltage outputs;   said first leg including a first current transistor and a switching transistor in series between the first voltage source and the first voltage output, and a first current limiting transistor coupled between the first voltage output and the second voltage source;   said second leg including a second current transistor coupled between the first voltage source and the first voltage output; and   said third leg including a third current transistor coupled between the first voltage source and the second voltage output, and a second current limiting transistor coupled between the second voltage output and the second voltage source.   
     
     
       15. The regulator of claim 14 wherein there is further provided a regulated voltage source coupled to and controlling said first and second current transistors. 
     
     
       16. The regulator of claim 14 wherein there is further provided a programmable means coupled to and controlling said switching transistor to permit current flow in said first leg. 
     
     
       17. The regulator of claim 16 wherein said switching transistor is coupled to said programmable source through an inverter circuit. 
     
     
       18. A regulator circuit comprising: first, second, and third current conducting legs;   first and second voltage sources;   first and second voltage outputs;   said first leg including a first current transistor coupled between the first voltage source and the first voltage output, and a first current limiting transistor coupled between the first voltage output and the second voltage source;   said second leg including a second current transistor coupled between the first voltage source and the first voltage output; and   said third leg including a third current transistor coupled between the first voltage source and the second voltage output, and a second current limiting transistor coupled between the second voltage output and the second voltage source; and   means for selectively switching said first leg into parallel to said second leg to vary the current applied to said first output.   
     
     
       19. The regulator circuit of claim 18 where said means for selectively switching said first leg comprises a switching transistor in series with said first current transistor and means of selectively switching said switching transistor from a conductive to a non-conductive state. 
     
     
       20. The circuit of claim 19 wherein there is further provided means for turning off said third and fourth current limiting, voltage controlled transistor and for turning off the current conducting transistor in said third leg. 
     
     
       21. The circuit of claim 16 wherein the first current conducting transistor of said first leg and said second current conducting transistor of said second leg each have their control electrode coupled to a regulated voltage source. 
     
     
       22. the circuit of claim 19 wherein said transistors are field effect transistors. 
     
     
       23. the circuit of claim 19 wherein said transistors are bipolar transistors.