Operational amplifier with offset compensation function

Abstract

An operational amplifier with an offset compensation function and a D/A converter employing the same for eliminating an offset voltage above a certain limit. In the operational amplifier, a current mirror is provided between a high voltage line and first and second nodes, and a current sink is provided between a third node and a low voltage line. A first transistor controls a current amount flowing from the first node to the third node, and a second transistor controls a current amount flowing the second node to the third node. An amplifier is connected between the second node and an output line to amplify a voltage signal of the output line. A mirror controller responds to the voltage signal from the output line to control the second transistor, and a sink controller responds to the voltage signal from the output line to control the current sink.

What is claimed is: 
     
       1. An operational amplifier with an offset compensation function, comprising: a current mirror provided between a high voltage line and first and second nodes;   a current sink provided between a third node and a low voltage line;   a first transistor, being responsive to an input signal, for controlling a current amount flowing from the first node into the third node;   a second transistor for controlling a current amount flowing the second node into the third node;   an amplifying unit connected between the second node and an output line to amplify an output signal from the second node; and   a mirror control unit, being responsive to a voltage signal output from the output line, for controlling the second transistor.   
     
     
       2. The operational amplifier as claimed in claim 1, further comprising: a sink control unit, being responsive to the voltage signal output from the output line, for controlling the current sink.   
     
     
       3. The operational amplifier as claimed in claim 2, wherein the current sink includes third and fourth transistors connected in parallel between the third node and the low level line to respond to an output signal of the sink control unit. 
     
     
       4. The operational amplifier as claimed in claim 3, wherein the third transistor is an NPN type thin film transistor and the fourth transistor is a PNP type thin film transistor. 
     
     
       5. The operational amplifier as claimed in claim 3, wherein the sink control unit includes: a first voltage sampler for sampling the voltage signal output from the output line and applying the sampled voltage signal to the third transistor; and   a second voltage sampler for sampling the voltage signal of the output line and applying the sampled voltage signal to the fourth transistor.   
     
     
       6. The operational amplifier as claimed in claim 5, wherein the first voltage sampler applies the sampled voltage signal, which has an increased voltage level than the voltage signal output from the output line, to the third transistor. 
     
     
       7. The operational amplifier as claimed in claim 5, wherein the first voltage sampler includes at least two capacitors connected in parallel to the output line and in series to the third transistor. 
     
     
       8. The operational amplifier as claimed in claim 5, wherein the second voltage sampler applies the sampled voltage signal to the fourth transistor, said sampled voltage signal having an increased voltage level and an opposite polarity compared to the voltage signal output from the output line. 
     
     
       9. The operational amplifier as claimed in claim 8, wherein the first voltage sampler includes at least two capacitors connected in parallel to the output line in a forward direction and in series to the fourth transistor in a reverse direction. 
     
     
       10. The operational amplifier as claimed in claim 1, wherein the sink control unit includes a voltage sampler for sampling the voltage signal from the output line, and applying the sampled voltage signal to the current sink. 
     
     
       11. The operational amplifier as claimed in claim 10, wherein the sampled voltage signal has an increased voltage level than the voltage signal output from the output line. 
     
     
       12. The operational amplifier as claimed in claim 1, wherein the mirror control unit includes a voltage sampler for sampling the voltage signal output from the output line and applying the sampled voltage signal to the second transistor. 
     
     
       13. The operational amplifier as claimed in claim 12, wherein the voltage sampler applies the sampled voltage signal to the second transistor, the sampled voltage signal having a polarity opposite to the voltage signal output from the output line. 
     
     
       14. A digital-to-analog converter, comprising: a decoding unit including input terminals for receiving at least two bit data and at least three output terminals to selectively output a signal from the at least three output terminals in accordance with a logical value of the data;   a first node commonly connected to the at least three output terminals of the decoding unit;   a current mirror provided between the first node and a high voltage line and a second node;   a current sink provided between a third node and a low voltage line;   a first transistor, being responsive to an input signal, for controlling a current amount flowing from the first node into the third node;   a second transistor for controlling a current amount flowing the second node into the third node;   an amplifying unit connected between the second node and an output line to amplify an output signal on the second node; and   a mirror control unit, being responsive to a voltage signal on the output line, for controlling the second transistor.   
     
     
       15. The digital-to-analog converter as claimed in claim 14, further comprising: at least three coupling capacitors between the at least three output terminal of the decoding unit and the first node, respectively.   
     
     
       16. The digital-to-analog converter as claimed in claim 14, wherein the mirror control unit includes a voltage sampler for sampling the voltage signal of the output line and applying the sampled voltage signal to the second transistor. 
     
     
       17. The digital-to-analog converter as claimed in claim 16, wherein the voltage sampler supplies the sampled voltage signal to the second transistor, the sampled voltage signal having a polarity opposite to the voltage signal of the output line. 
     
     
       18. The digital-to-analog converter as claimed in claim 14, further comprising: a sink control unit, being responsive to the voltage signal on the output line, for controlling the current sink.   
     
     
       19. The digital-to-analog converter as claimed in claim 18, wherein the sink control unit includes a voltage sampler for sampling the voltage signal of the output line and applying the sampled voltage signal to the current sink. 
     
     
       20. The digital-to-analog converter as clamed in claim 19, wherein said sampled voltage signal has an increase voltage level compared to the voltage signal of the output line. 
     
     
       21. The digital-to-analog converter as claimed in claim 18, wherein the current sink includes third and fourth transistors connected in parallel between the third node and the low voltage line to respond to an output signal of the sink control unit. 
     
     
       22. The digital-to-analog converter as claimed in claim 21, wherein the third transistor is an NPN type thin film transistor, and the fourth transistor is a PNP type thin film transistor. 
     
     
       23. The digital-to-analog converter as claimed in claim 21, wherein the sink control unit includes: a first voltage sampler for sampling the voltage signal of the output line, and applying the sampled voltage signal to the third transistor; and   a second voltage sampler for sampling the voltage signal of the output line, and applying the sampled voltage signal to the fourth transistor.   
     
     
       24. The digital-to-analog converter as claimed in claim 23, wherein the first voltage sampler applies the sampled voltage signal to the third transistor, said sampled voltage signal having a higher voltage level than the voltage signal of the output line. 
     
     
       25. The digital-to-analog converter as claimed in claim 23, wherein the first voltage sampler includes at least two capacitors connected in parallel to the output line and in series to the third transistor. 
     
     
       26. The digital-to-analog converter as claimed in claim 23, wherein the second voltage sampler applies the sampled voltage signal to the fourth transistor, said sampled voltage signal having a higher voltage level and an opposite polarity compared to the voltage signal of the output line. 
     
     
       27. The digital-to-analog converter as claimed in claim 26, wherein the first voltage sampler includes at least two capacitors connected in parallel to the output line in a forward direction and in series to the fourth transistor in a reverse direction.