Composite metal films for severe topology interconnects

Abstract

A process for forming a smooth conformal refractory metal film on an insulating layer having a via formed therein. This process provides extremely good planarity and step coverage when used to form contacts in semiconductor circuits and, in addition, offers improved wafer alignment capability as well as enhanced reliability which result from the smooth surface morphology. The process includes forming contact openings through an insulating layer to a semiconductor substrate; depositing a first blanket layer of titanium using deposition conditions that provide a conformal film that exhibits good step coverage at the contact opening; and forming a second blanket layer of titanium using deposition conditions that provide reduced surface asperity height. The process is ideally suited to forming an electrical interconnection system for semiconductor integrated circuit devices such as static or dynamic random access memories and is particularly useful in VLSI devices that incorporate multiple levels of interconnect.

We claim: 
     
       1. A conductor comprising: a first conductive layer having a first surface asperity; and   a second conductive layer formed on said first conductive layer and having a surface asperity which is less than said first surface asperity.   
     
     
       2. A conductor as recited in claim 1 wherein said first and second conductive layers comprise tungsten. 
     
     
       3. A conductor as recited in claim 1 wherein said first and second conductive layers have a thickness that is about half that of said conductor. 
     
     
       4. A conductor as recited in claim 1 wherein said first conductive layer is formed on a nucleating layer. 
     
     
       5. A conductor as recited in claim 4 wherein said nucleating layer comprises titanium tungsten. 
     
     
       6. A structure on a semiconductor substrate, said structure comprising: a first insulating layer formed on said substrate and having at least one via therein;   a first conductive layer formed on said substrate and in said via, said first conductive layer conformally covering said via and having a first asperity height; and   a second conductive layer formed on said first conductive layer, said second conductive layer having a substantially planer upper surface, said upper surface having a surface asperity height which is less than said first asperity height.   
     
     
       7. A structure as recited in claim 6 wherein said first insulating layer comprises: a first dielectric layer over said substrate; and   a second dielectric layer over said first insulating layer.   
     
     
       8. A structure as recited in claim 7 wherein said second dielectric layer is an oxide doped with phosphorus. 
     
     
       9. A structure as recited in claim 6 and further comprising: a second insulating layer overlying said second conductive layer, said second insulating layer having a second via formed therein;   a third conductive layer overlying said second insulating layer and in said second via; and   a fourth conductive layer overlying said third conductive layer.   
     
     
       10. A structure as recited in claim 6 wherein said first conductive layer has a thickness about at least half that of the diameter of the largest via in said first insulating layer.