Redundant decision circuit for semiconductor memory device

Abstract

A redundancy decision circuit for specifying a redundant memory cell in a memory cell array when a normal cell is defective. The circuit includes a switching element, a fuse and a load circuit connected in series between high and low potential supplies. A switching driver drives the switching element. A hold circuit latches the potential at a node between the switching element and one of either the fuse and the load circuit. The circuit then generates a redundant decision signal.

What is claimed is: 
     
       1. A redundant decision circuit, comprising: a switching element;   a switching driver connected to the switching element for driving the switching element;   a fuse;   a load circuit connected in series with the fuse, wherein one of the fuse and the load circuit is connected to the switching element; and   a hold circuit, connected to a node between the switching element and one of the fuse and the load circuit, for latching a potential at the node and generating a redundant decision signal, wherein the switching element is a P-channel MOS transistor and the load circuit is a P-channel MOS transistor the gate of which is connected to a low potential power supply.   
     
     
       2. The circuit of claim 1, wherein the load circuit generates a voltage drop in accordance with a current flowing in the fuse. 
     
     
       3. A redundant decision circuit, comprising: a switching element connected between a high potential power supply and a node;   a switching driver connected to the switching element for driving the switching element;   a fuse;   a load circuit connected in series with the fuse between a low potential power supply and the node; and   a hold circuit, connected to the node, for latching a potential at the node and generating a redundant decision signal.   
     
     
       4. The circuit of claim 3, wherein the load circuit generates a voltage drop in accordance with a current flowing in the fuse. 
     
     
       5. The circuit of claim 3, wherein the switching element is a P-channel MOS transistor and the load circuit is a P-channel MOS transistor the gate of which is connected to the low potential power supply. 
     
     
       6. The circuit of claim 3, wherein the switching element is a P-channel MOS transistor and the load circuit is two series connected P-channel MOS transistors the gates of which are connected to the low potential power supply. 
     
     
       7. The circuit of claim 3, wherein the switching element is a P-channel MOS transistor and the load circuit is a resistor. 
     
     
       8. The circuit of claim 3, wherein the switching element is a P-channel MOS transistor and the load circuit is a diode. 
     
     
       9. A semiconductor memory device, comprising: a memory cell array including a normal cell array and a redundant cell array;   a redundant decision circuit for generating a redundant decision signal; and   a decoder, connected to the redundant decision circuit, for performing a redundant operation to select a normal cell of the normal cell array or a redundant cell of the redundant cell array in accordance with the redundant decision signal, the redundant decision circuit including, a switching element,   a switching driver connected to the switching element for driving the switching element,   a fuse,   a load circuit connected in series with the fuse, one of the fuse and the load circuit being connected to the switching element, and   a hold circuit, connected to a node between the switching element and one of the fuse and the load circuit, for latching a potential at the node and generating the redundant decision signal.     
     
     
       10. A semiconductor memory device, comprising: a memory cell array including a normal cell array and a redundant cell array;   a redundant decision circuit for generating a redundant decision signal; and   a decoder, connected to the redundant decision circuit, for performing a redundant operation to select a normal cell of the normal cell array or a redundant cell of the redundant cell array in accordance with the redundant decision signal, the redundant decision circuit including, a switching element connected between a high potential power supply and a node,   a switching driver connected to the switching element for driving the switching element,   a fuse,   a load circuit connected in series with the fuse between a low potential power supply and the node, and   a hold circuit, connected to the node, for latching a potential at the node and generating the redundant decision signal.     
     
     
       11. A method for deciding redundancy, comprising the steps of: connecting a fuse, a load circuit and a switching element in series between a high potential power supply and a low potential power supply;   driving the switching element to generate a potential at a node between the switching element and the fuse, the potential at the node varying by a voltage drop generated by the load circuit; and   holding the potential at the node to generate a redundant decision signal.   
     
     
       12. A method for deciding redundancy, comprising the steps of: connecting a switching element to a high potential power supply;   connecting a fuse and a load circuit in series between the switching element and a low potential power supply;   driving the switching element to generate a potential at a node between the switching element and the fuse, the potential at the node increasing by a voltage drop generated by the load circuit; and   holding the potential at the node to generate a redundant decision signal.   
     
     
       13. A redundant decision circuit comprising: a switching element;   a switching driver connected to the switching element for driving the switching element;   a fuse;   a load circuit connected in series with the fuse, wherein one of the fuse and the load circuit is connected to the switching element; and   a hold circuit, connected to a node between the switching element and one of the fuse and the load circuit, for latching a potential at the node and generating a redundant decision signal, wherein the switching element is a P-channel MOS transistor and the load circuit is two series connected P-channel MOS transistors the gates of which are connected to a low potential power supply.   
     
     
       14. A redundant decision circuit comprising: a switching element;   a switching driver connected to the switching element for driving the switching element;   a fuse;   a load circuit connected in series with the fuse, wherein one of the fuse and the load circuit is connected to the switching element; and   a hold circuit, connected to a node between the switching element and one of the fuse and the load circuit, for latching a potential at the node and generating a redundant decision signal, wherein the switching element is a P-channel MOS transistor and the load circuit is a resistor.   
     
     
       15. A redundant decision circuit comprising: a switching element;   a switching driver connected to the switching element for driving the switching element;   a fuse;   a load circuit connected in series with the fuse, wherein one of the fuse and the load circuit is connected to the switching element; and   a hold circuit, connected to a node between the switching element and one of the fuse and the load circuit, for latching a potential at the node and generating a redundant decision signal, wherein the switching element is a P-channel MOS transistor and the load circuit is a diode.