Semiconductor device with fast write recovery circuit

Abstract

A semiconductor memory device including a fast write recovery circuit. The semiconductor memory device has a memory array, a sense amplifier and the fast write recovery circuit. Before the end of a precharging operation, a last bit of data is written into a memory cell of the memory by the sense amplifier, as well as by the fast write recovery circuit from the other end. Thus, the time required for writing the last bit of data is shortened to prevent from writing a fragmental data into the memory cell in a transient write cycle. Furthermore, a write operation with a high speed can be executed with being restricted by layout.

What is claimed is: 
     
       1. A semiconductor memory device including a fast write recovery circuit, comprising: a memory array, including a plurality of memory cells coupled to a pair of bit lines;   a sense amplifier, connecting across the pair of bit lines and a pair of data lines to write data of the pair of data lines into the memory cells of the memory array; and   the fast write recovery circuit, including a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, wherein   Source regions of the first and the fourth PMOS transistors are to receive a write signal, a gate of the first PMOS transistor is coupled to drain regions of the third and the fourth PMOS transistors, a gate of the fourth PMOS transistor is coupled to drain regions of the first and the second PMOS transistors, gates of the second and the third PMOS transistors are to receive a self time pulse signal WRB, and source regions of the second and the third PMOS transistors are coupled to the pair of the bit lines, respectively, and   wherein when the sense amplifier writes a last bit of data, the write signal is written into the memory cell from the fast write recovery circuit at the same time.   
     
     
       2. The semiconductor memory device according to claim 1, wherein the fast write recovery circuit further comprises a circuit to generate the self time pulse signal WRB, the circuit to generate the self time pulse signal WRB comprising: an NAND gate, with two input terminals to receive a SLFR+CBR signal and a SAE signal;   a first inverter, with an input terminal coupled to an output terminal of the NAND gate;   a first delay circuit, with an input terminal coupled to an output terminal to the first inverter;   a first NOR gate, with two input terminals coupled to an output terminal of the first delay circuit and to receive a GWEP signal;   a second delay circuit, with an input terminal coupled to an output terminal of the NOR gate;   a second NOR gate, with two input terminals coupled to the second delay circuit and the output terminal of the first NOR gate; and   a second inverter, with an input terminal coupled to an output terminal of the second NOR gate and an output terminal to output the self time pulse signal WRB.   
     
     
       3. The circuit to generate the self time pulse signal WRB according to claim 2, wherein the first delay circuit comprises an even number of series-connected inverters. 
     
     
       4. The circuit to generate the self time pulse signal WRB according to claim 2, wherein the second delay circuit comprises an odd number of series-connected inverters. 
     
     
       5. The semiconductor memory device according to claim 1, wherein the self time pulse signal WRB is in a low potential level during a write cycle, while the self time pulse signal WRB is in a high potential level during a read cycle. 
     
     
       6. The semiconductor memory device according to claim 1, wherein the semiconductor memory device includes a dynamic random access memory. 
     
     
       7. A semiconductor memory device, comprising: a memory array, including a plurality of memory cells;   a sense amplifier, connecting across a pair of bit lines and a pair of data lines; and   a fast write recovery circuit; wherein   while the sense amplifier is writing a last bit of data into a memory cell, the fast write recovery circuit write a write signal into the memory cell at the same time.   
     
     
       8. The semiconductor memory device according to claim 7, further comprising a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, wherein Source regions of the first and the fourth PMOS transistors are to receive a write signal, a gate of the first PMOS transistor is coupled to drain regions of the third and the fourth PMOS transistors, a gate of the fourth PMOS transistor is coupled to drain regions of the first and the second PMOS transistors, gates of the second and the third PMOS transistors are to receive a self time pulse signal WRB, and source regions of the second and the third PMOS transistors are coupled to the pair of the bit lines, respectively.   
     
     
       9. The semiconductor memory device according to claim 8, wherein the fast write recovery circuit further comprises a circuit to generate a self time pulse signal WRB, the circuit to generate the self time pulse signal WRB comprising: an NAND gate, with input terminals to receive a SLFR+CBR signal and a SAE signal;   a first inverter, with an input terminal coupled to an output terminal of the NAND gate;   a first delay circuit, with an input terminal coupled to an output terminal to the first inverter;   a first NOR gate, with input terminals coupled to an output terminal of the first delay circuit and to receive a GWEP signal;   a second delay circuit, with an input terminal coupled to an output terminal of the NOR gate;   a second NOR gate, with input terminals coupled to the second delay circuit and the output terminal of the first NOR gate; and   a second inverter, with an input terminal coupled to an output terminal of the second NOR gate and an output terminal to output the self time pulse signal WRB.