Selectable delay circuit having immunity to variations in fabrication and operating condition for write precompensation in a read/write channel

Abstract

Precompensated NRZ-encoded data for writing to magnetic storage medium operates with multiple NRZI-to-NRZ decoders that are each supplied with a selectably-variable version of a master clock. The delayed versions of the master clock are stably produced by delay elements operating with D-flip flops and charge pumps in a delay-locked feedback loop. The direction of current supplied to or from a capacitor by the charge-pump during a cycle of delayed clock signal is controlled by the delayed clock signal for shaping the feedback signal to trigger appropriately the next cycle of the delayed clock signal. The duration of the selectable delay is adjusted by setting the amplitudes of the charge and discharge currents supplied by the charge-pump. Stable delayed versions of the master clock promote reliable conversions of NRZI data to write precompensated NRZ recordable data.

We claim: 
     
       1. A circuit for supplying a selected duration of delay with respect to transitions of a clock signal from a first state to a second state, the circuit comprising: a delay cell having inputs connected to receive the clock signal and a feedback signal, and being disposed to supply a third signal at an output port thereof having third and fourth states, said delay cell delaying transitions from the third state to the fourth state by a selected duration with respect to transitions of the clock signal from the first state to the second state in response to the average voltage of the feedback signal;   a charge pump having inputs connected to receive the third signal and a control signal for specifying the selected duration, and having an output connected to supply current in a direction responsive to the state of the third signal and with an amplitude related to the control signal; and   a capacitor connected to receive the current from the charge pump for supplying the feedback signal as the voltage across the capacitor.   
     
     
       2. The circuit of claim 1, wherein the delay cell decreases the duration of delay in response to an increase in the average voltage of the feedback signal. 
     
     
       3. The circuit of claim 1, wherein the delay cell increases the duration of delay in response to an increase in the average voltage of the feedback signal. 
     
     
       4. The circuit of claim 1, wherein the charge pump receives the control signal in digital form representing a number Y inclusively between zero and one, and wherein the charge-pump further comprises: a first current mirror connected to continuously supply a first current of amplitude Y×I at the output of the charge pump for charging the capacitor at one rate during the third state of the third signal; and   a second current mirror connected to draw a second current of amplitude I from the output of the charge pump during the fourth state of the third signal, for discharging the capacitor at another rate during said fourth state.   
     
     
       5. The circuit of claim 4, wherein the third state is represented by a low voltage, the fourth state is represented by a high voltage, the charging rate is determined by Y×I, and the discharging rate is determined by (1-Y)×I. 
     
     
       6. The circuit of claim 1 wherein the delay cell comprises: a field-effect transistor having a gate connected to receive the feedback signal, a source coupled to a first voltage, and a drain connected to supply a variable voltage in response to the average voltage of the feedback signal;   an inverter having an input connected to receive the clock signal, and having an output for supplying an inverted clock signal with trailing edges which fall at a rate responsive to a voltage differential between the drain of the field effect transistor and a second voltage; and   a comparing gate having inputs connected to receive the clock and fourth signals, and having an output disposed to supply the third signal in response to the states of the clock and fourth signals.   
     
     
       7. The circuit of claim 6, wherein the comparing gate comprises: a buffer having an input connected to receive the fourth signal, and having an output connected to supply a fifth signal with rapidly falling edges which fall in response to the gradually falling edges of the fourth signal reaching a sufficiently low voltage; and   a NAND gate connected to receive the fifth signal and the clock signal for supplying the third signal as a logical combination of the fifth and clock signals received thereby.   
     
     
       8. The circuit of claim 6, wherein the delay cell further comprises a predriver having an input port connected to receive an applied clock signal, and having an output for supplying the clock signal with a longer duty cycle than the applied clock signal to enable the comparing gate to supply delays of longer duration. 
     
     
       9. The circuit of claim 1, further comprising a flip-flop circuit having a data input connected to receive a digital signal synchronized with the clock signal, having a clock input connected to receiving the third signal from the delay cell and triggered by transitions from the third state to the fourth state thereof, and having an output connected to supply a delayed digital signal that is delayed by said selected duration with respect to the digital signal. 
     
     
       10. The circuit of claim 8, wherein the third state is represented by a low voltage, the fourth state is represented by a high voltage, and wherein the flip-flop is positive edge triggered. 
     
     
       11. A circuit for providing write precompensation for a data storage device, the circuit comprising: a plurality of the circuits of claim 8, each disposed to receive a digital signal for data storage, and each connected to receive a control signal specifying different durations of delay; and   a mulitplexer having a plurality of input ports, each input port coupled to said output port of a distinct one of the circuits of claim 8 for receiving a distinct one of a plurality of fourth signals therefrom, the multiplexer having a selection port for receiving a selection signal to control selection of one of the input ports thereof, and having an output for supplying the fourth signal corresponding to said one of the input ports.   
     
     
       12. A method for supplying a delayed clock signal having third and fourth states, and transitions between the third state and the fourth state delayed by a selected duration with respect to transitions of a clock signal between a first state and a second state, the method using a capacitor and comprising the steps of: receiving the clock signal;   forming a feedback signal representative of voltage across the capacitor;   generating the delayed clock signal having transitions between the third and fourth states delayed with respect to state transitions of the clock signal between the first and second states in response to the feedback signal;   receiving a control signal indicating a selected duration of delay;   generating a flow of current having a direction determined by the states of the third signal and having an amplitude responsive to the selected duration of delay specified by the control signal; and   supplying the flow of current to the capacitor to provide the feedback signal representative of voltage across the capacitor.   
     
     
       13. The method of claim 12, further comprising the steps of: receiving a digital signal synchronized with the clock signal; and   supplying a delayed digital signal having state transitions delayed by a second duration of delay with respect to the state transitions of applied signal.   
     
     
       14. A circuit for code converting a digital signal, that is synchronized with a clock signal, the circuit operating on a delayed clock signal that is delayed by a predetermined duration with respect to the clock signal, the circuit comprising: a multiplexer having a first input coupled to receive a first signal, a second input coupled to receive an inverted first signal, a selection input coupled to receive the digital signal for selecting one of the received first and inverted first signals to supply as an intermediate signal at an output of the multiplexer; and   a flip flop having an input coupled to the output of the multiplexer for receiving the intermediate signal, a clock input coupled to receive the delayed clock signal for triggering the flip flop to supply the first signal to the first input of the multiplexer in response to the flip flop being triggered, and for supplying the inverted first signal to the second input of the multiplexer in response to the flip flop being triggered to provide the code converted digital signal as one of the first and inverted first signals.   
     
     
       15. The circuit of claim 14, wherein the flip flop comprises a positive edge triggered D-flip flop for synchronizing transitions in the first signal with respect to rising edges of the delayed clock signal for digital signals synchronized with respect to rising edges of the clock signal. 
     
     
       16. A method for code converting a digital signal synchronized with a clock signal in a circuit including a multiplexer, a D-type flip flop, the method comprising: triggering the D-type flip flop in response to an applied signal to produce an output signal and an inverted output signal synchronized with respect to the clock signal;   selecting in the multiplexer one of the output signal and inverted output signal in response to the digital signal as a selection input to the multiplexer to provide an output of the multiplexer as the applied signal for triggering the D-type flip flop to produce the code converted digital signal as one of the output and inverted output signals.   
     
     
       17. The method of claim 16 wherein the D-type flip flop is triggered on positive edges of the clock signal in response to the applied signal from the output of the multiplexer.