Computational field programmable architecture

Abstract

A computational field programable architecture targeted for compute intensive applications. The architecture is hierarchical and includes, for implementation of data path circuits, clusters of programable logic blocks that are designed to provide area-efficient realization of common arithmetic structures such as adders, subtracters and multipliers. The architecture includes a LUTb cluster for implementing the control part of a circuit. The programable logic blocks each include a stack of programable bit-slice logic elements each having 2 data inputs and a single data output, and a 1-bit full adder circuit. The bit slice logic elements allow bit-wise logic operations to be carried out and the programable logic blocks also include comparator logic to enable comparison operations to be performed. The bit slice logic elements each include a DFF at their output, and the DFFs in a programable logic blocks can be combined to form a register. The inputs of each of the programable logic blocks are connected to cluster level tracks through a partially populated crossbar.

We claim: 
     
       1. A field programmable architecture for compute-intensive applications, comprising: a section level interconnect channel;   a first logic cluster for implementing control logic, comprising a plurality of logic blocks interconnected by a local interconnect channel that is in communication with said section level interconnect channel; and   a second logic cluster for implementing data path operations, comprising a plurality of programable logic blocks interconnected by a cluster level interconnect channel that is in communication with said section level interconnect channel,   said programable logic blocks each configured to perform operations on two N-bit operands and comprising: (a) a stack of N bit-slice logic elements each having two data bit inputs, a data bit output a multiply bit input, a carry-in bit input a carry-out bit output a programable operation select circuit for processing inputs received by said two data bit inputs and said multiply bit input, and a 1-bit full adder circuit for generating a sum-bit output and said carry-bit output in response to information received from said operation select circuit and said carry-in bit input the carry-in bit input of each successive bit slice logic element being connected to the carry-out bit output of the preceding bit-slice logic element; and   (b) control means for programming the operation select circuits of each of said bit slice logic elements in order to selectively configure said programmable logic block to implement one of a ripple carry adder subtracter and partial multiplier,     said programable logic blocks of said second logic cluster having a different configuration than the logic blocks of said first logic cluster such that said programable logic blocks provide a more area-efficient realization of adders, subtracters and partial multipliers than the logic blocks of said first logic cluster.   
     
     
       2. The field programable architecture according to claim 1 wherein the programable operation select circuit of each of said bit-slice logic elements includes a plurality of multiplexers, and said control means includes a plurality of programable SRAM cells operatively connected to said multiplexers. 
     
     
       3. The field programmable architecture according to claim 2 wherein each of said bit-slice logic elements includes an output logic circuit having an output multiplexer with a plurality of inputs, one of said inputs being connected to a sum-bit output of said adder circuit, said control means including means for selecting the output provided by the output multiplexer of the output logic circuit of each of said bit-slice elements. 
     
     
       4. The field programmable architecture according to claim 3 wherein said programable logic block includes comparator logic connected to said bit slice logic elements for generating logic outputs based on the relative values of said two N-bit operands, said comparator logic having different output lines for different logic comparisons, said output lines each being connected as an input to the output multiplexer of a different one of said bit-slice elements. 
     
     
       5. The field programmable architecture according to claim 1 wherein the value of N is within the range of 2 to 6. 
     
     
       6. The field programmable architecture according to claim 1 including a plurality of said second logic clusters, wherein the logic blocks of said first logic cluster are Look Up Table logic blocks. 
     
     
       7. A programmable logic block that can be configured to perform addition, subtraction and partial multiplication on two N-bit operands, comprising: (a) a stack of N bit-slice logic elements, each having two data bit inputs, a data bit output, a multiplier bit input, a carry-in bit input, and a carry-out bit output, the carry-in bit input of each successive bit-slice logic element being connected to the carry-out bit output of the preceding bit-slice logic element, each of said bit-slice elements including (i) a 1-bit full adder circuit for generating a sum-bit output on said data bit output and having carry logic connected to receive said carry-in bit input and generate an output on said carry-out bit output; and   (ii) a programable operation select circuit connected to said 1-bit full adder circuit for selectively processing data received on said two data bit inputs and said multiplier control bit input, and providing said selectively processed data to said adder circuit, said operation select circuit of each of said bit-slice logic elements being programable such that said stack of bit-slice logic elements can selectively implement adders, subtracters and partial multipliers; and     (b) control means for programming the operation select circuit of each of said bit-slice logic elements.   
     
     
       8. The programable logic block according to claim 7 wherein said operation select circuit includes a by-passable AND gate which allows an input signal on said multiply-bit input to be ANDed with an input signal on one of said two data bit inputs when said programable logic block is configured to perform partial multiplication. 
     
     
       9. The programmable logic block according to claim 8 wherein said full adder circuit of each of said bit slice elements comprises a first XOR gate and a second XOR gate, the output of said first XOR gate and said carry-in input being the inputs of said second XOR gate, the output of said second XOR gate generating the sum-bit output of said adder, the output of said by-passable AND gate being connected to an input of said first XOR gate. 
     
     
       10. The programable logic block according to claim 9 wherein said programable operation select circuit includes a plurality of control multiplexers, and said control means including a plurality of SRAM cells, wherein each of said SRAM cells is operatively connected to said control multiplexers in each of said N-bit slices. 
     
     
       11. The programmable logic block according to claim 9 wherein each of said bit-slice logic elements includes an output logic circuit having an output select multiplexer with a plurality of inputs, one of said inputs being connected to receive the sum-bit output of said adder circuit and the output of said output select multiplexer being in communication with said data bit output, said control means including means for selecting the output provided by the output select multiplexer of each of said bit-slice logic elements. 
     
     
       12. The programable logic block according to claim 11 including a comparator logic circuit connected to each of said bit-slice logic elements for generating logic outputs based on the relative values of said two N-bit operands, said comparator logic circuit having different output lines for different logic comparisons, said output lines each being connected as an input to the output select multiplexer of a different one of said bit-slice elements. 
     
     
       13. The programable logic block according to claim 12 wherein the output circuit of each of said bit-slice elements includes a D flip-flop connected to the output of said output select multiplexer, and a switch for connecting the output of said D flip flop or the direct output of said output multiplexer to said data bit output, thereby enabling the stack of N bit-slice logic elements to function as a shift register. 
     
     
       14. The programmable logic block according to claim 11 wherein said logic block is nibble controlled and includes four of said bit-slice elements. 
     
     
       15. A programmable logic cluster for implementing data path operations comprising: a plurality of programable logic blocks for performing operations on 2 N-bit operands, said programable logic blocks each having 2 sets of N data bit inputs, a carry-in bit input, a multiply bit input, a carry-out bit output and a set of N data bit outputs, and including N bit-slice logic elements for performing bit-wise operations on said operands, and a comparator logic circuit connected to each of said bit-slice logic elements for generating logic outputs based on the relative values of the 2 N-bit operands, said programable logic blocks being programmable to realize adders, subtracters, and partial multipliers; and   a cluster level interconnect channel interconnecting said plurality of programable logic blocks, having a plurality of cluster level tracks connected to the inputs of each of said programable logic blocks through switches located on a partially populated crossbar.   
     
     
       16. A programable logic cluster for implementing data path operations comprising: a plurality of programable logic blocks for performing operations on 2 N-bit operands, said programable logic blocks each having 2 sets of N data bit inputs, a carry-in bit input, a multiply bit input, a carry-out bit output and a set of N data bit outputs, and including N bit-slice logic elements for performing bit-wise operations on said operands, said programable logic blocks being programable to realize adders, subtracters, and partial multipliers;   a cluster level interconnect channel interconnecting said plurality of programable logic blocks, having a plurality of cluster level tracks connected to the inputs of each of said programable logic blocks through switches located on a partially populated crossbar, said cluster level tracks being connected to said inputs by routing multiplexers; and   dedicated routing lines between adjacent programable logic blocks for implementing multipliers and fast adders.   
     
     
       17. The programable logic cluster according to claim 1 wherein N is 4.