Method of manufacturing semiconductor device for preventing electrostatic discharge

Abstract

A method of manufacturing a semiconductor device for preventing ESD damage is disclosed. A semiconductor device for preventing against ESD damage according to a first embodiment of the present invention, is fabricated as follows. Firstly, first impurity ions of a first conductivity type are implanted into a first region of a substrate of a semiconductor device using a first ion implantation, to form a first impurity ion layer. Here, a junction region will be formed in the first region and is connected to an input pad. Second impurity ions of the first conductivity type are then implanted into a second region of the substrate using a second ion implantation, to form a second impurity ion layer over the first ion impurity ion layer. Here, the second region includes the first region. Next, third impurity ions of a second conductivity type are implanted into the substrate of both sides of the first and second impurity ion layers, using a third ion implantation, to form a third impurity ion layer. The resultant structure is then annealed to form a first well for ESD of the first conductivity type and a second well of the second conductivity type. Here, the second well joins to the first well, and the upper edges of the first well is projected into the second well. Thereafter, junction regions of the first conductivity type of a high concentration are formed on the first and second wells.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device adapted to be inserted between an input pad and an inside circuit for protection against an electrostatic discharge generating from the input pad, said method comprising the steps of: implanting first impurity ions of a first conductivity type into a substrate so as to form a first impurity ion layer below a location at which a junction region connected to the input pad is to be formed;   implanting second impurity ions of the first conductivity type into said substrate so as to form a second impurity ion layer interposed between said first impurity ion layer and said location, said first impurity ion layer being overlapped laterally with said second impurity ion layer;   implanting third impurity ions of a second conductivity type into said substrate so as to form third impurity ion layers, each of which is located on a lateral side of said first and second impurity ion layers; and   forming a first well and second wells from said first and second impurity ion layers and said third impurity ion layers, respectively, through an annealing process such that said first well is formed with upper edges, each of which projects laterally outwardly into a corresponding one of said second wells.   
     
     
       2. A method of manufacturing a semiconductor device adapted to be inserted between an input pad and an inside circuit for protection against an electrostatic discharge generating from the input pad, said method comprising the steps of: implanting first impurity ions of a first conductivity type into a first region of a substrate so as to form a first impurity ion layer therein below a first location at which a first junction region connected to the input pad is to be formed, said first region spanning laterally between said first location and a second location at which a second junction region connected to an associated power source is to be formed;   implanting second impurity ions of a second conductivity type into a second region of said substrate so as to form a second impurity ion layer therein, said second region being located laterally outwardly from said first region; and   annealing said substrate so as to form a first well from said first impurity ion layer for preventing electrostatic discharge damage and so as to form a second well from said second impurity ion layer, said second well being confined to said second region such that it is located apart from said first well and such that it is not adjoined with said first well.   
     
     
       3. A method of manufacturing a semiconductor device adapted to be inserted between an input pad and an inside circuit for protection against an electrostatic discharge generating from the input pad, said method comprising the steps of: providing a substrate having therein a first well of a first conductivity type for preventing electrostatic discharge damage and a second well of a second conductivity type, said first well being adjoined with said second well such that an upper edge of said second well projects laterally outwardly into said first well;   implanting impurity ions of the first conductivity type of a high concentration into said substrate so as to form first and second impurity ion layers directly above said first and second wells, respectively, without implanting said impurity ions into said upper edge; and   annealing said substrate so as to form first and second junction regions from said first and second impurity ion layers, respectively, said first junction region being adjoined to said first well and connected to the input pad.   
     
     
       4. The method of claim 1, wherein said second impurity ion layer is formed with a lateral width greater than that of said first impurity ion layer during said second impurity ion implanting step. 
     
     
       5. The method of claim 4, further comprising the steps of forming a first mask pattern on said substrate prior to said first impurity ion implanting step so as to expose a first region of said substrate such that said first impurity ions can be implanted into said first region during said first impurity ion implanting step; and forming a second mask pattern on said substrate prior to said second impurity ion implanting step so as to expose a second region of said substrate such that said second impurity ions can be implanted into said second region during said second impurity ion implanting step, said first region being overlapped laterally with said second region and having a lateral width smaller than that of said second region. 
     
     
       6. The method of claim 2, further comprising the steps of forming a first mask pattern on said substrate prior to said first impurity ion implanting step so as to expose a third region of said substrate such that said first impurity ions can be implanted into said third region during said first impurity ion implanting step, said third region being contained within said first region; and forming a second mask pattern on said substrate prior to said second impurity ion implanting step so as to expose said second region without exposing said first region and said third region. 
     
     
       7. The method of claim 3, further comprising the step of forming a mask pattern on said substrate prior to said impurity ion implanting step so as to laterally cover said upper edge such that said impurity ions are inhibited from being implanted into said upper edge during said impurity ion implanting step. 
     
     
       8. The method of claim 1, further comprising the steps of forming junction regions of the first conductivity type of a high concentration on the first and second wells. 
     
     
       9. The method of claim 2, further comprising the steps of forming junction regions of the first conductivity type of a high concentration on the first and second well. 
     
     
       10. The method of claim 2, wherein the first and second ion implantation steps are performed by a step-by-step implantation of the first and second impurity ions, respectively, based upon the depth of the substrate.