PLL Circuit in which output oscillation signal frequency can be controlled based on bias signal

Abstract

In a phase locked loop (PLL) circuit, a phase comparator compares an input signal and a feed back signal in phase to generate a phase difference voltage signal. A loop filter filters the phase difference voltage signal, and generates a filter output voltage signal. A bias signal generating section automatically generates a bias signal. A voltage controlled oscillating section generates an oscillation output signal based on the filter output voltage signal and the bias signal. The voltage controlled oscillating section generates the oscillation output signal having a same frequency as that of the input signal based on the bias signal. A counter generates the feed back signal based on the oscillation output signal.

What is claimed is: 
     
       1. A phase locked loop (PLL) circuit comprising: a first phase comparator for comparing an input signal and a first feed back signal in phase to generate a first phase difference voltage signal;   a first loop filter for filtering said first phase difference voltage signal, and for generating a first filter output voltage signal;   a bias signal generating section for generating a bias signal;   a first voltage controlled oscillating section for generating a first oscillation output signal based on said first filter output voltage signal and said bias signal, wherein said voltage controlled oscillating section generates said first oscillation output signal having a same frequency as that of said input signal based on said bias signal; and   a first counter for generating said first feed back signal based on said first oscillation output signal, and   wherein said bias signal generating section includes;   a second phase comparator for comparing a reference input signal and a second feed back signal in phase to generate a second phase difference voltage signal;   a second loop filter for filtering said second phase difference voltage signal, and for generating a second filtered output voltage signal;   a second voltage controlled oscillating section for generating a second oscillation output signal and said bias signal based on said second filtered output voltage signal; and   a second counter for generating said second feed back signal based on said second oscillation output signal, and   wherein said first voltage controlled oscillating section includes;   a first voltage/current converter for converting said first filtered output voltage signal into a first phase error current signal;   an adder for adding said first phase error current signal and said bias signal to generate a control signal; and   a first current controlled oscillator for generating said first oscillation output signal based on said control signal, and   wherein said second voltage controlled oscillating section includes;   a second voltage/current converter for converting said second filtered output voltage signal into a second phase error current signal and said bias signal and for supplying said bias signal to said adder; and   a second current controlled oscillator for generating said second oscillation output signal based on said second phase error current signal.   
     
     
       2. A PLL circuit according to claim 1, wherein said first current controlled oscillator and said second current controlled oscillator receive same influence of temperature and same influence in manufacturing processes, and change characteristics in same degrees due to the received influence. 
     
     
       3. A PLL circuit according to claim 1, wherein said first and second oscillation output signals have a same frequency. 
     
     
       4. A PLL circuit according to claim 1, wherein said first counter frequency-divides said first oscillation output signal with a ratio of 1/M (M is a positive number), and said second counter frequency-divides said second oscillation output signal with a ratio of 1/N (N is a positive number). 
     
     
       5. A PLL circuit according to claim 4, wherein said reference input signal has a frequency of (N/M) times of that of said input signal. 
     
     
       6. A PLL circuit according to claim 1, wherein said first and second loop filters are low pass filters, and a cut-off frequency of said first filter is lower than that of said second filter. 
     
     
       7. A PLL circuit according to claim 1, wherein said first voltage controlled oscillating section has a gain larger than that of said second voltage controlled oscillating section. 
     
     
       8. A PLL circuit according to claim 1, wherein said first and second current controlled oscillators have a same gain, and wherein said second voltage/current converter converts said second filtered output voltage signal into said first phase error current signal and said bias signal with a conversion efficiency higher than that of said first voltage/current converter when said first voltage/current converter converts said first filter output voltage signal into said first phase error current signal. 
     
     
       9. A phase locked loop (PLL) circuit comprising: a bias signal generating section for generating a bias signal, wherein said bias signal generating section comprises:   a first phase comparator for comparing a reference input signal and a first feed back signal in phase to generate a first phase difference voltage signal,   a first loop filter for filtering said first phase difference voltage signal to pass a component of a first frequency range, and for generating a first filtered output voltage signal,   a first voltage controlled oscillating section for generating a first oscillation output signal and said bias signal based on said first filtered output voltage signal, and   a first counter for generating said first feed back signal based on said first oscillation output signal;   a second phase comparator for comparing an input signal and a second feed back signal in phase to generate a first phase difference voltage signal;   a second loop filter for filtering said second phase difference voltage signal to pass a component of a first frequency range, and for generating a first filtered output voltage signal;   a second voltage controlled oscillating section for generating a second oscillation output signal based on said second filtered output voltage signal and said bias signal; and   a second counter for generating said second feed back signal based on said second oscillation output signal, and   wherein said first voltage controlled oscillating section includes;   a first voltage/current converter for converting said first filtered output voltage signal into a first phase error current signal and said bias signal and for supplying said bias signal to said second voltage controlled oscillating section; and   a first current controlled oscillator for generating said first oscillation output signal based on said first phase error current signal; and   wherein said second voltage controlled oscillating section includes;   a second voltage/current converter for converting said second filtered output voltage signal into a second phase error current signal;   an adder for adding said second phase error current signal and said bias signal from said first voltage/current converter to generate a control signal; and   a second current controlled oscillator for generating said second oscillation output signal based on said control signal.   
     
     
       10. A PLL circuit according to claim 9, wherein said second voltage controlled oscillating section generates said second oscillation output signal having a same frequency as that of said input signal based on said bias signal. 
     
     
       11. A PLL circuit according to claim 9, wherein said first and second oscillation output signals have a same frequency. 
     
     
       12. A PLL circuit according to claim 11, wherein said first counter frequency-divides said first oscillation output signal with a ratio of 1/M (M is a positive number), and said second counter frequency-divides said second oscillation output signal with a ratio of 1/N (N is a positive number). 
     
     
       13. A PLL circuit according to claim 12, wherein said reference input signal has a frequency of (N/M) times of that of said input signal. 
     
     
       14. A PLL circuit according to claim 9, wherein said first and second filters are low pass filters, and a cut-off frequency of said second filter is lower than that of said first filter. 
     
     
       15. A PLL circuit according to claim 9, wherein said first voltage controlled oscillating section has a gain larger than that of said second voltage controlled oscillating section. 
     
     
       16. A PLL circuit according to claim 15, wherein said first and second current controlled oscillators have a same gain, and wherein said first voltage/current converter converts said first filtered output voltage signal into said first phase error current signal and said bias signal with a conversion efficiency higher than that of said second voltage/current converter when said second voltage/current converter converts said second filtered output voltage signal into said second phase error current signal. 
     
     
       17. A PLL circuit comprising: a first phase comparator for comparing an input signal and a first feedback signal in phase to generate a first phase difference voltage signal;   a first loop filter for filtering said first phase difference voltage signal to generate a first filtered output voltage signal;   a first voltage/current converter for converting said first filtered output voltage signal into a first phase error current signal;   a bias adjusting circuit for generating a bias current signal;   a current adder for adding said first phase error current signal and said bias current signal to generate a first oscillator control current signal;   a first current controlled oscillator for oscillating based on said first oscillator control current signal to generate a first oscillator output signal; and   a first frequency divider for frequency-dividing a frequency of said first oscillator output signal into 1/N (N is a positive number) to generate said first feedback signal;   wherein said bias adjusting circuit includes: a second phase comparator for comparing a reference clock signal and a second feedback signal in phase to generate a second phase difference voltage signal;   a second loop filter for filtering said second phase difference voltage signal to generate a second filtered output voltage signal;   a second voltage/current converter for converting said second filtered output voltage signal into a second phase error current signal;   a second current controlled oscillator for oscillating based on said second oscillator control current signal to generate a second oscillator output signal; and   a second frequency divider for frequency-dividing a frequency of said second oscillator output signal into 1/M (M is a positive number) to generate said second feedback signal.