Adjustable serial-to-parallel or parallel-to-serial converter

Abstract

A clock synchronizer may include two programmable counters, one which may be programmed with a bit-rate value so that it generates a signal approximately matching the bit rate of the asynchronous data signal, and the other programmed with a phase-delay value so that it generates a sample clock signal at a phase delay from the signal generated by the first counter. The phase of the sample clock may be adjusted by restarting the counters in response to a transition on the asynchronous data signal. Data may be supplied to a serial-to-parallel converter including a first shift register configured to shift a data word in serially and output the data word in parallel and a second shift register configured to track when the data word had been completely shifted into the first shift register and to cause the data word to be outputted in parallel from the first shift register so that a new word may be shifted into the first shift register. A status value may be loaded into the second shift register so that when the last bit is converted in the first shift register, the second shift register shifts out a conversion completed indication. The bit length to be converted may be changed by loading a different status value into the second shift register. This same technique may be employed in a parallel-to-serial data converter or in a general data converter that may convert from serial-to-parallel or parallel-to-serial according to a conversion-type signal.

I claim:  
     
       1. A parallel-to-serial converter, comprising: 
       a first shift register configured to receive a data word in parallel and shift out said data word serially; and  
       a second shift register configured to track when said data word has been completely shifted out of said first shift register and to cause a new data word to be loaded in parallel into said first shift register.  
     
     
       2. The parallel-to-serial converter as recited in claim  1 , wherein said second shift register is loaded with a value corresponding to the number of bits in said data word. 
     
     
       3. The parallel-to-serial converter as recited in claim  2 , wherein said value is shifted in said second shift register each time a bit of said data word is shifted out of said first shift register so that a load indication is shifted out of said second shift register when the last bit of said data word is shifted out of said first shift register. 
     
     
       4. The parallel-to-serial converter as recited in claim  1 , wherein said first shift register is configured to convert data words of varying bit lengths from parallel-to-serial format, wherein the bit-size of said first shift register is equal to the maximum bit length to be converted. 
     
     
       5. The parallel-to-serial converter as recited in claim  4 , wherein said second shift register is adapted to track different bit lengths by receiving a shift status word corresponding to the bit length of the data word to be converted. 
     
     
       6. The parallel-to-serial converter as recited in claim  5 , wherein the bit-length to be converted may be changed dynamically. 
     
     
       7. A serial-to-parallel converter, comprising: 
       a first shift register configured to shift in a data word serially and output said data word in parallel; and  
       a second shift register configured to track when said data word has been completely shifted into said first shift register and to cause said data word to be outputted in parallel from said first shift register.  
     
     
       8. The serial-to-parallel converter as recited in claim  7 , wherein said second shift register is loaded with a value corresponding to the number of bits in said data word. 
     
     
       9. The serial-to-parallel converter as recited in claim  8 , wherein said value is shifted in said second shift register each time a bit of said data word is shifted into said first shift register so that an output indication is shifted out of said second shift register after the last bit of said data word is shifted into said first shift register. 
     
     
       10. The serial-to-parallel converter as recited in claim  7 , wherein said first shift register is configured to convert data words of varying bit lengths from serial-to-parallel format, wherein the bit-size of said first shift register is equal to the maximum bit length to be converted. 
     
     
       11. The serial-to-parallel converter as recited in claim  10 , wherein said second shift register is adapted to track different bit lengths by receiving a shift status word corresponding to the bit length of the data word to be converted. 
     
     
       12. The serial-to-parallel converter as recited in claim  11 , wherein the bit-length to be converted may be changed dynamically. 
     
     
       13. A data converter, comprising: 
       a first shift register configured to perform a data conversion by shifting in a data word serially and outputting said data word in parallel or receiving said data word in parallel and shifting out said data word serially, as determined by a direction signal; and  
       a second shift register configured to track when said data conversion has been completed and to cause said data conversion to be performed on a next data word.  
     
     
       14. The data converter as recited in claim  13 , wherein said second shift register is loaded with a value corresponding to the number of bits in said data word. 
     
     
       15. The data converter as recited in claim  14 , wherein said value is shifted in said second shift register each time a bit of said data word is shifted into or out of said first shift register so that a conversion complete indication is shifted out of said second shift register when the last bit of said data word is converted in said first shift register. 
     
     
       16. The data converter as recited in claim  13 , wherein said first shift register is configured to convert data words of varying bit lengths, wherein the bit-size of said first shift register is equal to the maximum bit length to be converted. 
     
     
       17. The data converter as recited in claim  16 , wherein said second shift register is adapted to track different bit lengths by receiving a shift status word corresponding to the bit length of the data word to be converted. 
     
     
       18. The data converter as recited in claim  17 , wherein the bit-length to be converted may be changed dynamically. 
     
     
       19. A method for tracking the conversion of a data word from parallel-to serial or serial-to-parallel format, comprising: 
       shifting a data word into or out of a first shift register, according to a conversion-type indication;  
       shifting a value in a second shift register each time data in said first shift register is shifted; and  
       outputting a conversion complete indication from said second shift register when said conversion is complete.  
     
     
       20. The method as recited in claim  19 , further comprising loading said second shift register with a value corresponding to the number of bits in said data word. 
     
     
       21. The method as recited in claim  19 , further comprising converting a new data word in response to said conversion complete indication. 
     
     
       22. The method as recited in claim  19 , wherein said first shift register is configured to convert data words of varying bit lengths, wherein the bit-size of said first shift register is equal to the maximum bit length to be converted. 
     
     
       23. The method as recited in claim  22 , further comprising loading a shift status word into said second shift register corresponding to the bit length of the data word to be converted. 
     
     
       24. The method as recited in claim  19 , further comprising dynamically changing the data word bit-length to be converted.