Method for filling structural gaps and intergrated circuitry

Abstract

A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.

What is claimed is:  
     
       1. A semiconductor processing method for filling structural gaps comprising: 
       providing a pair of wordline constructions over a semiconductive material substrate, the wordline constructions being separated by a gap and exposing semiconductive material therebetween;  
       depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over the exposed semiconductive material between the wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions; and  
       depositing a layer of a boron containing silicon oxide comprising material on the substantially boron free silicon oxide comprising material and over the wordline constructions.  
     
     
       2. The method of claim  1 , wherein the pair of wordline constructions comprise conductive gates having sidewalls which are at least partially covered with silicon nitride and which border at least a portion of the gap. 
     
     
       3. The method of claim  2 , wherein the silicon nitride covers at least a majority portion of the gate sidewalls and borders at least a majority portion of the gap. 
     
     
       4. The method of claim  2 , wherein a bottom border of the gap is defined entirely by the semiconductive material and side borders of the gap are defined entirely by silicon nitride encapsulation of the wordline constructions. 
     
     
       5. The method of claim  1 , wherein the semiconductive material comprises silicon. 
     
     
       6. The method of claim  1 , wherein the depositing the substantially boron free material comprises a sub-atmospheric chemical vapor deposition (SACVD). 
     
     
       7. The method of claim  6 , wherein the SACVD deposition occurs at a pressure of about 400 to 760 Torr and a temperature of about 350 to 600 Celsius (° C.) while providing about 200 to 800 milligram/minute (mg/min) of a tetraethylorthosilicate comprising liquid and providing about 4.5 to 7 standard liters/minute (slm) of an ozone and oxygen comprising gas. 
     
     
       8. The method of claim  1 , wherein the boron free material comprises undoped silicon dioxide or phosphosilicate glass. 
     
     
       9. The method of claim  8 , wherein the boron free material comprises phosphosilicate glass and completely fills the gap. 
     
     
       10. The method of claim  1 , wherein the boron free material does not completely fill the gap. 
     
     
       11. The method of claim  1 , wherein the second average deposition rate is initially approximately zero Å/min and begins to increase after a time delay. 
     
     
       12. The method of claim  11 , wherein the time delay is greater than 5 seconds. 
     
     
       13. The method of claim  11 , wherein the time delay is greater than 100 seconds. 
     
     
       14. The method of claim  1 , wherein the depositing a boron containing material occurs at the same deposition rate over the gap and the wordlines. 
     
     
       15. The method of claim  1 , wherein the boron containing material comprises a borophosphosilicate glass (BPSG). 
     
     
       16. A semiconductive processing method for filling structural gaps comprising: 
       forming a device structure having a gap at least partially bordered by silicon nitride and that exposes an underlying silicon comprising substrate, the gap having a first aspect ratio;  
       depositing a substantially boron free silicon oxide comprising material substantially selectively, at least initially, to the silicon substrate to form a reduced gap having a second aspect ratio less than or equal to the first aspect ratio; and  
       depositing a layer of boron containing silicon oxide comprising material on the substantially boron free silicon oxide comprising material and over the device structure.  
     
     
       17. The method of claim  16 , wherein the device structure is comprised of a pair of spaced conductive device components at least partially encapsulated by silicon nitride. 
     
     
       18. The method of claim  17 , wherein at least a majority portion of each sidewall of the gap is lined with the silicon nitride. 
     
     
       19. The method of claim  17 , wherein the conductive device components comprise conductive polysilicon comprising lines. 
     
     
       20. The method of claim  17 , wherein a bottom border of the gap is defined entirely by the silicon substrate and side borders of the gap are defined entirely by silicon nitride encapsulation of the conductive device components. 
     
     
       21. The method of claim  16 , wherein depositing a boron free material comprises a SACVD. 
     
     
       22. The method of claim  16 , wherein the boron free material comprises undoped silicon dioxide or phosphosilicate glass. 
     
     
       23. The method of claim  16 , wherein the boron containing material comprises a BPSG. 
     
     
       24. A semiconductor processing method for filling structural gaps comprising: 
       providing a pair of wordline constructions over a silicon substrate, the wordline constructions being separated by a gap and exposing the silicon substrate therebetween;  
       depositing a substantially boron free silicon oxide comprising material substantially selectively, at least initially, to the silicon substrate in a thermal chemical vapor deposition chamber; and  
       depositing in situ in the chamber, a BPSG on the silicon oxide comprising material.  
     
     
       25. The method of claim  24 , wherein the pair of wordline constructions comprise conductive gates having sidewalls which are at least partially covered with silicon nitride and which border at least a portion of the gap. 
     
     
       26. The method of claim  25 , wherein the silicon nitride covers at least a majority portion of the gate sidewalls and borders at least a majority portion of the gap. 
     
     
       27. The method of claim  25 , wherein a bottom border of the gap is defined entirely by the silicon substrate and side borders of the gap are defined entirely by silicon nitride encapsulation of the wordline constructions. 
     
     
       28. The method of claim  24 , wherein the depositing a boron free material comprises a SACVD. 
     
     
       29. The method of claim  24 , wherein the boron free material comprises silicon dioxide or phosphosilicate glass. 
     
     
       30. The method of claim  24 , wherein the boron free material does not completely fill the gap. 
     
     
       31. The method of claim  24 , wherein the deposition of the boron free material initially occurs substantially selectively to the silicon when compared to deposition on a silicon nitride layer received over the pair of wordlines. 
     
     
       32. The method of claim  31 , wherein the deposition occurs on the silicon compared to the silicon nitride at an average selectivity ratio greater than 1. 
     
     
       33. The method of claim  24 , wherein the depositing the BPSG occurs at the same deposition rate over the gap and the wordlines. 
     
     
       34. A semiconductor processing method for filling structural gaps comprising: 
       providing a pair of wordline constructions over a silicon substrate, the wordline constructions being separated by a gap exposing the silicon substrate therebetween and comprising silicon nitride which at least partially lines the gap; and  
       depositing a substantially boron free silicon oxide comprising material at a first deposition rate over the silicon substrate within the gap and at a second deposition rate over the wordline constructions, wherein, at least initially, the first deposition rate is greater than the second deposition rate.  
     
     
       35. The method of claim  34 , wherein the silicon nitride lines at least a majority of the gap. 
     
     
       36. The method of claim  34 , wherein a bottom border of the gap is defined entirely by the silicon substrate and side borders of the gap are defined entirely by the silicon nitride encapsulation. 
     
     
       37. The method of claim  34 , further comprising depositing a boron containing silicon oxide comprising material on the boron free silicon oxide comprising material. 
     
     
       38. The method of claim  34 , wherein the step of depositing a boron free material comprises a SACVD. 
     
     
       39. The method of claim  34 , wherein the boron free material comprises undoped silicon dioxide or phosphosilicate glass. 
     
     
       40. The method of claim  34 , wherein the boron free material does not completely fill the gap. 
     
     
       41. The method of claim  34 , wherein the boron free material completely fills the gap. 
     
     
       42. The method of claim  41 , wherein the boron free material comprises phosphosilicate glass. 
     
     
       43. The method of claim  34 , wherein the second deposition rate is initially approximately zero Å/min and increases to the first deposition rate after a time delay. 
     
     
       44. The method of claim  43 , wherein the time delay is greater than 5 seconds. 
     
     
       45. The method of claim  43 , wherein the time delay is greater than 100 seconds.