Off-grid metal layer utilization

Abstract

Routing of electrical connections between cells arranged in cell columns on an integrated circuit (IC) die. Electrical connections are routed on a routing layer between cells located in a first cell column. An identification is made of an available off-grid resource capable of being used for wire routing that is both within the first cell column and on the routing layer. An electrical connection is routed between a first cell and a second cell located in different cell columns using at least a portion of the identified available off-grid resource. Also, an integrated circuit die which includes vertical power rails and vertical ground rails. Cell columns, including a first cell column and a second cell column, are each bordered by a vertical power rail and a vertical ground rail. A channel is provided between the first cell column and the second cell column. An electrical connection is provided between a first electronic component in the first cell column and a second electronic component in the second cell column. The electrical connection includes an on-grid wire segment in the channel between the first cell column and the second cell column and an off-grid wire segment formed in one of the cell columns.

What is claimed is:  
     
       1. A method for routing electrical connections between cells arranged in cell columns on an integrated circuit (IC) die, said method comprising: 
       an intra-column routing step of routing electrical connections on a routing layer between cells located in a first cell column;  
       an identifying step of identifying an available resource capable of being used for wire routing that is both within the first cell column and on the routing layer; and  
       an inter-column routing step of routing an electrical connection between a first cell and a second cell located in different cell columns using at least a portion of the available resource identified in said identifying step,  
       wherein said inter-column routing step comprises a global routing step of performing a rough routing between the first cell and the second cell by generating a pseudo-pin in a channel between the first cell and the second cell.  
     
     
       2. A method according to claim  1 , wherein said inter-column routing step comprises a pseudo-pin moving step of moving the pseudo-pin to a new location in the channel by routing an electrical connection between an original location of the pseudo-pin and the new location, using the available resource identified in said identifying step. 
     
     
       3. A method according to claim  2 , wherein the new location is determined based on the position of at least one of the first cell and the second cell. 
     
     
       4. A method according to claim  2 , wherein said inter-column routing step comprises a detailed routing step of routing electrical connections between the first cell and the pseudo-pin and between the pseudo-pin and the second cell. 
     
     
       5. A method according to claim  4 , wherein the detailed routing step is performed after the pseudo-pin moving step. 
     
     
       6. A method according to claim  1 , wherein the first cell column is bordered by power/ground rails, and wherein said identifying step is performed by: (1) locating a horizontal position x within the first cell column at which a wire could be placed without violating a minimum spacing requirement from the power/ground rails, and then (2) by considering at least one additional spacing requirement, identifying a range of vertical positions y where each (x,y) is a valid position for a wire. 
     
     
       7. A method according to claim  6 , wherein the horizontal position x is a horizontal position which is closest to one of the power/ground rails without violating the minimum spacing requirement from the power/ground rails. 
     
     
       8. A method according to claim  1 , wherein the routing layer is a metal layer closest to a semiconductor layer of the die. 
     
     
       9. A method according to claim  1 , wherein said inter-column routing step performs grid-based routing. 
     
     
       10. A method for routing electrical connections between cells arranged in cell columns on an integrated circuit (IC) die, said method comprising: 
       an intra-column routing step of routing electrical connections on a routing layer between cells located in a first cell column;  
       an identifying step of identifying an available resource capable of being used for wire routing that is both within the first cell column and on the routing layer; and  
       an inter-column routing step of routing an electrical connection between a first cell and a second cell located in different cell columns, using grid-based routing in a channel between the first cell and the second cell and using at least a portion of the available resource identified in said identifying step  
       wherein said inter-column routing step comprises a global routing step of performing a rough routing between the first cell and the second cell and a detailed routing step of performing exact routing between the first cell and the second cell based on an output of the global routing step, and  
       wherein said inter-column routing step further comprises a preprocessing step of preprocessing the output of the global routing step by utilizing the available resource identified in said identifying step so as to reduce a task of the detailed routing step.  
     
     
       11. A method according to claim  10 , wherein the preprocessing step comprises moving a pseudo-pin generated in said global routing step. 
     
     
       12. A method according to claim  10 , wherein the detailed routing step directly utilizes the available resource identified in said identifying step. 
     
     
       13. A method according to claim  1 , wherein said identifying step identifies the available resource without regard to any routing grid. 
     
     
       14. A method according to claim  10 , wherein said identifying step identifies the available resource without regard to any routing grid.