Address generator display and spatial light modulator

Abstract

An address generator for a display or spatial light modulator, comprising a first shift register having a plurality of cascade-connected stages for controlling respective first address electrodes of the display or spatial light modulator. The stages of the first shift register include a first reconfigurable shift register stage which is selectively operable in an alternate mode, in which the output of the first reconfigurable shift register stage follows the output of a preceding stage.

What is claimed is:  
     
       1. An address generator for a display or spatial light modulator, comprising a first shift register having a plurality of cascade-connected stages for controlling respective first address electrodes of the display or spatial light modulator, 
       wherein the stages of the first shift register include a first reconfigurable shift register stage which is selectively operable in an alternate mode, in which the output of the first reconfigurable shift register stage follows the output of a preceding stage, and  
       further wherein the first reconfigurable shift register stage and the preceding stage control adjacent first electrodes and the output of the first reconfigurable shift register stage follows the output of the preceding stage in the alternate mode so as to display the same visual data in two or more adjacent first address electrodes.  
     
     
       2. An address generator as claimed in claim  1 , wherein the first shift register is an analog shift register. 
     
     
       3. An address generator as claimed in claim  1 , wherein the first shift register is a digital shift register. 
     
     
       4. A spatial light modulator comprising an address generator as claimed in claim  1 . 
     
     
       5. A spatial light modulator as claimed in claim  4 , being of matrix type. 
     
     
       6. A spatial light modulator as claimed in claim  5 , being of active matrix type. 
     
     
       7. A spatial light modulator as claimed in claims  4 , being of liquid crystal type. 
     
     
       8. A display comprising an address generator as claimed in claim  1 . 
     
     
       9. A display as claimed in claim  8 , being of matrix type. 
     
     
       10. A display as claimed in claim  9 , being of active matrix type. 
     
     
       11. A display as claimed in claim  8 , being of liquid crystal type. 
     
     
       12. An address generator for a display or spatial light modulator, comprising a first shift register having a plurality of cascade-connected stages for controlling respective first address electrodes of the display or spatial light modulator, 
       wherein the stages of the first shift register include a first reconfigurable shift register stage which is selectively operable in an alternate mode, in which the output of the first reconfigurable shift register stage follows the output of a preceding stage,  
       further wherein each stage of the first shift register comprises:  
       a first memory having a first memory enable input connected to a first phase of a first bi-phase clock line, and  
       a second memory having a second memory enable input connected to a second phase of the first bi-phase clock line,  
       wherein the first memory enable input of the first reconfigurable shift register stage of the first shift register being selectively connectable to the second phase of the first bi-phase clock line.  
     
     
       13. An address generator as claimed in claim  12 , wherein each of the first and second memories comprises a bi stable circuit. 
     
     
       14. An address generator as claimed in claim  12 , wherein each of the stages subsequent to a first stage of the first shift register comprises a switch for selectively connecting the first memory enable input to the first or second phase of the first bi-phase clock line. 
     
     
       15. An address generator as claimed in claim  14 , further comprising a first further shift register having a plurality of cascade-connected stages for controlling respective ones of the switches of the first shift register. 
     
     
       16. An address generator for a display or spatial light modulator, comprising a first shift register having a plurality of cascade-connected stages for controlling respective first address electrodes of the display or spatial light modulator, 
       wherein the stages of the first shift register include a first reconfigurable shift register stage which is selectively operable in an alternate mode, in which the output of the first reconfigurable shift register stage follows the output of a preceding stage,  
       further wherein the first shift register comprises:  
       a first sub-shift register having a first plurality of cascade-connected sub-stages, and  
       a second sub-shift register having a second plurality of cascade-connected sub-stages,  
       wherein the first plurality of sub-stages being interlaced with the second plurality of sub-stages.  
     
     
       17. An address generator for a display or spatial light modulator, comprising a first shift register having a plurality of cascade-connected stages for controlling respective first address electrodes of the display or spatial light modulator, 
       wherein the stages of the first shift register include a first reconfigurable shift register stage which is selectively operable in an alternate mode, in which the output of the first reconfigurable shift register stage follows the output of a preceding stage,  
       further comprising a second shift register having a plurality of cascade-connected stages for controlling respective second address electrodes of the display or spatial light modulator, the stages of the second shift register including a second reconfigurable shift register stage which is selectively operable in the alternate mode.  
     
     
       18. An address generator as claimed in claim  17 , wherein the second shift register is an analog shift register. 
     
     
       19. An address generator as claimed in claim  17 , wherein the second shift register is a digital shift register. 
     
     
       20. An address generator as claimed in claims  17 , wherein each stage of the second shift register comprises; 
       a third memory having a third memory enable input connected to a first phase of a second bi-phase clock line, and  
       a fourth memory having a fourth memory enable input connected to a second phase of the second bi-phase clock line,  
       wherein the third memory enable input of the second reconfigurable shift register stage of the second shift register being selectively connectable to the second phase of the second bi-phase clock line.  
     
     
       21. An address generator as claimed in claim  20 , wherein each of the third and fourth memories comprises a bistable circuit. 
     
     
       22. An address generator as claimed in claim  20 , wherein each of the stages of the second shift register subsequent to a first stage thereof comprises a switch for selectively connecting the third memory enable input to the first or second phase of the second bi-phase clock line. 
     
     
       23. An address generator as claimed in claim  22 , further comprising a second further shift register having a plurality of cascade-connected stages for controlling respective ones of the switches of the second shift register.