Apparatus for determining the instantaneous average number of instructions processed

Abstract

An apparatus is provided for determining an average number of instructions entering a stage of a processor pipeline of a computer system during a clock cycle of a processor clock. The number of instructions entering a particular stage of the pipeline are stored in a queue during each of a predetermined number (N) of clock cycles. The total number of instructions processed over the last P clock cycles is computed, where P is less than or equal to N. The total number of instructions processed is divided by the last P processor cycles to yield the instantaneous average number of instructions processed for each processor cycle. This average number of instructions processed is communicated to software.

We claim:  
     
       1. An apparatus for determining an average number of instructions entering a stage of a processor pipeline of a computer system during a clock cycle of a processor clock, comprising: 
       means for storing the number of instructions entering a particular stage of the pipeline during each of a predetermined number (N) of clock cycles;  
       means for computing the total number of instructions processed over the last P clock cycles, where P is less than or equal to N;  
       means for dividing the total number of instructions processed by the last P processor cycles to yield the instantaneous average number of instructions processed for each processor cycle; and  
       means for communicating the average number of instructions processed to software.  
     
     
       2. The apparatus of claim  1  wherein the pipeline includes a plurality of stages. 
     
     
       3. The apparatus of claim  2  wherein the plurality of stages include fetch, map, issue, execute, and retire stages. 
     
     
       4. The apparatus of claim  1  wherein the particular stage is any one of fetch, map, issue, execute, or retire stages. 
     
     
       5. The apparatus of claim  1  wherein the means for storing includes a first-in-first-out queue with room for N values and with new values added to a head of the queue and old values removed from a tail of the queue. 
     
     
       6. The apparatus of claim  5  wherein each entry in the queue records the number of instructions entering a particular stage of the pipeline during a single clock cycle. 
     
     
       7. The apparatus of claim  6  wherein a current total of the numbers stored in the entries of the queue is stored in a register. 
     
     
       8. The apparatus of claim  7  wherein the current total is maintained in each clock cycle by adding, the number of the entry addedd at the head of the queue and subtracting the number stored in the entry removed from the tail of the queue. 
     
     
       9. The apparatus of claim  1  wherein the instantaneous average number of instructions processed for each processor cycle is part of the state information of the computer system. 
     
     
       10. The apparatus of claim  9  wherein the instantaneous average is communicated to software while sampling processor states during the execution of a particular selected instruction. 
     
     
       11. The apparatus of claim  1  wherein the means for communicating the average to software includes of a special instruction that stores the average into an architectural register or a memory location. 
     
     
       12. The apparatus of claim  1  wherein P is fixed to be equal to N by hardware. 
     
     
       13. The apparatus of claim  1  wherein P is specified by software to be in the range from 1 to N.