Single ended dual port memory cell

Abstract

A method of reading the contents of a dual port memory cell which has a Beta Ratio less than 1.5 is described. A wordline is associated with a selected port of the memory cell. The wordline is coupled to a gate device of the memory cell for controlling communication between the memory cell and a bitline. The gate device has a first conductance at a first wordline voltage and a second conductance at a second wordline voltage. The second conductance is less than the first conductance. A port of the cell is selected by applying a select voltage to the associated wordline. The select voltage is approximately the same as the second wordline voltage. The cell contents are then retrieved from the bitline.

What is claimed is:  
     
       1. A method of reading a value stored in a single ended dual port memory cell, said method comprising the steps of: 
       (a) selecting a wordline associated with a selected port of the memory cell having a Beta Ratio less than 1.5, wherein the wordline is coupled to a gate device for controlling communication between the memory cell and a bitline, wherein the gate device has a first conductance at a first wordline voltage and a second conductance at a second wordline voltage, wherein the second conductance is less than the first conductance;  
       (b) applying a select voltage to the wordline, wherein the select voltage is approximately the same as the second wordline voltage; and  
       (c) retrieving the value from the bitline.  
     
     
       2. The method of claim  1  wherein the first wordline voltage is substantially the same as a supply voltage for the memory cell.