System and method for generating error checking data in a communications system

Abstract

A circuit and method for generating cyclic redundancy check (CRC) data is disclosed. In one embodiment, the circuit interfaces with a data bus with other processor components. The circuit includes an input first-in-first-out (FIFO) to interface with the data bus, a configuration register electrically coupled to the data bus, and a configurable CRC generation circuit electrically coupled to the data bus and to the configuration register. The CRC generation circuit includes a bit shift register which is configurable to generate CRC data for multiple protocols. To accomplish this, the bit shift register is configurable for different lengths, the actual length of the bit shift register being determined by the data communication protocols employed.

Having thus described the invention, it is claimed:  
     
       1. A cyclic redundancy check (CRC) generator circuit, comprising: 
       an input first-in-first-out (FIFO) to interface with a data bus;  
       a configuration register electrically coupled to the data bus, the configuration receiving a configuration data signal from the data bus; and  
       a configurable CRC generation circuit electrically coupled to the data bus, the configurable CRC generation circuit having a shift register with a plurality of register positions, wherein data can be written to and read from the register positions via the data bus.  
     
     
       2. The cyclic redundancy check (CRC) generator circuit of claim  1 , wherein the configurable CRC circuit further comprises: 
       a first modulo-2 circuit having a data input and a feedback data input, and an output, the output of the first modulo-2 circuit being applied to the shift register; and  
       an order selection circuit which determines an order of the CRC generation circuit.  
     
     
       3. The cyclic redundancy check (CRC) generator circuit of claim  2 , wherein the shift register length selection circuit further comprises: 
       a feedback multiplexer having at least two feedback inputs, a feedback output applied to the feedback data input of the first modulo-2 circuit, and a feedback selection control input to cause one of the feedback inputs to be applied to the feedback selection output; and  
       a plurality of predetermined register position outputs being applied to the feedback multiplexer inputs, wherein the number of register positions employed in calculating a CRC data value being determined by a control signal applied to the feedback multiplexer control input.  
     
     
       4. The cyclic redundancy check (CRC) generator circuit of claim  2 , further comprising a circuit configured to control an application of any combination of a number of polynomial coefficients to the CRC generation circuit. 
     
     
       5. The cyclic redundancy check (CRC) generator circuit of claim  3 , further comprising: 
       a gated clocking input to each register position, the clocking input triggering the shifting of data;  
       a gating logic device to disable the clocking input to register position not employed in calculating the CRC data value.  
     
     
       6. The cyclic redundancy check (CRC) generator circuit of claim  3 , further comprising at least one asynchronous transfer mode (ATM) divider circuit for dividing the shift register into a predetermined number of header error checksum generating circuits. 
     
     
       7. A cyclic redundancy check (CRC) generator circuit, comprising: 
       means for receiving a data input from a data bus;  
       means for generating a CRC configuration control signal based upon a predetermined data communications protocol; and  
       means for generating CRC data based upon the CRC configuration control signal, the CRC data being transmitted to the data bus.  
     
     
       8. The cyclic redundancy check (CRC) generator circuit of claim  7 , wherein the means for generating CRC data further comprises: 
       first means for performing a modulo-2 operation between the data input and a feedback data input;  
       a shift register having a predetermined number of register positions, the output of the first means being applied to the shift register; and  
       second means for determining a number of register positions employed in calculating a CRC data value.  
     
     
       9. The cyclic redundancy check (CRC) generator circuit of claim  8 , wherein the means for determining a number of register positions further comprises: 
       a feedback multiplexer (MUX) having at least two feedback MUX inputs, a feedback MUX output applied to the feedback data input of the first XOR gate, and, a feedback MUX control input to cause one of the feedback MUX inputs to be applied to the feedback MUX output; and  
       predetermined register position outputs being applied to the feedback MUX inputs, the number of register positions employed in calculating a CRC data value being determined by a control signal applied to the feedback MUX control input.  
     
     
       10. A cyclic redundancy check (CRC) generator circuit, comprising the steps of: 
       receiving a data input from a data bus;  
       generating a CRC configuration control signal based upon the data input using a predetermined data communications protocol; and  
       generating CRC data based upon the CRC configuration control signal, the CRC data being transmitted to the data bus.  
     
     
       11. The method of claim  10 , wherein the step of generating CRC data further comprises: 
       performing a modulo-2 operation between the data input and a feedback data input;  
       determining a number of register positions employed in calculating a CRC data value in a bit shift register having a predetermined number of register positions; and  
       generating CRC data using the number of a register positions, the output of the first XOR gate being applied to the shift register.