Bus system for use with information processing apparatus

Abstract

A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and controL buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

What is claimed is:  
     
       1. An information processing system comprising: 
       a processor bus, said processor bus for transferring address, and control signals;  
       a processor coupled to said processor bus;  
       a cache memory directly coupled to said processor;  
       a memory bus, said memory bus for transferring data, address, and control signals;  
       a main memory coupled to said memory bus;  
       a system bus, said system bus for transferring data, address and control signals; and  
       a device coupled to said system bus;  
       wherein said information processing system enables a transfer of data between any two of said processor, said main memory and said device via corresponding two of said processor bus, said memory bus and said system bus.  
     
     
       2. An information processing system according to claim  1 , wherein 
       each of said processor bus, said memory bus, and said system bus includes a data bus for transferring said data, an address bus for transferring said address, and a control bus for transferring said control signals.  
     
     
       3. An information processing system according to claim  2 , wherein at least one of said processor bus, said memory bus, and said system bus is an address/data multiplexed type. 
     
     
       4. An information processing system according to claim  1 , wherein at least one of said processor bus, said memory bus, and said system bus is an address/data multiplexed type. 
     
     
       5. An information processing system according to claim  1 , wherein said device is a controller for displaying images. 
     
     
       6. An information processing system comprising: 
       a first bus to be coupled to a processor which is directly coupled to a cache, said first bus transferring data, address, and control signals;  
       a second bus to be coupled to a memory, said second bus transferring data, address, and control signals; and  
       a third bus to be coupled to a device, said third bus transferring data, address, and control signals;  
       wherein said information processing system enables a transfer of data between any arbitrary two of said processor, said memory and said device via corresponding two of said first bus, said second bus and said third bus.  
     
     
       7. An information processing system according to claim  6 , wherein 
       each of said first bus, said second bus, and said third bus includes a data bus for transferring said data, an address bus for transferring said address, and a control bus for transferring said control signals.  
     
     
       8. An information processing system according to claim  7 , wherein at least one of said first bus, said second bus, and said third bus is an address/data multiplexed type. 
     
     
       9. An information processing system according to claim  6 , wherein at least one of said first bus, said second bus, and said third bus is an address/data multiplexed type. 
     
     
       10. An information processing system according to claim  6 , wherein said device is a controller for displaying images. 
     
     
       11. An information processing system according to claim  6 , wherein said first bus is a processor bus, 
       wherein said second bus is a memory bus, and  
       wherein said third bus is a system bus.  
     
     
       12. An information processing system comprising: 
       a processor bus, said processor bus for transferring address and control signals;  
       a plurality of processors coupled to said processor;  
       a plurality of cache memories, each of said cache memories being directly coupled to each of said processors;  
       a memory bus, said memory bus for transferring data, address, and control signals;  
       a main memory coupled to said memory bus;  
       an I/O bus, said I/O bus for transferring data, address and control signals; and  
       a device coupled to said I/O bus;  
       wherein said information processing system enables a transfer of data between any arbitrary two of said main memory, said device and one of said processors via corresponding two of said processor bus, said memory bus and said I/O bus.  
     
     
       13. An information processing system according to claim  12 , wherein 
       each of said processor bus, said memory bus, and said I/O bus has a data bus for transferring said data, an address bus for transferring said address, and a control bus for transferring said control signals.  
     
     
       14. An information processing system according to claim  13 , wherein at least one of said processor bus, said memory bus, and said I/O bus is an address/data multiplexed type. 
     
     
       15. An information processing system according to claim  12 , wherein at least one of said processor bus, said memory bus, and said I/O bus is an address/data multiplexed type. 
     
     
       16. An information processing system comprising: 
       a processor bus, said processor bus for transferring data, address, and control signals;  
       a processor coupled to said processor bus;  
       a cache memory directly coupled to said processor;  
       a memory bus, said memory bus for transferring data, address, and control signals;  
       a main memory coupled to said memory bus;  
       an I/O bus, said I/O bus for transferring data, address, and control signals; and  
       a display control device coupled to said I/O bus;  
       wherein said information processing system enables a transfer of data between any arbitrary two of said processor, said main memory and said display control device via corresponding two of said processor bus, said memory bus and said I/O bus.  
     
     
       17. An information processing system according to claim  16 , wherein 
       each of said processor bus, said memory bus, and said I/O bus has a data bus for transferring said data, an address bus for transferring said address, and a control bus for transferring said control signals.  
     
     
       18. An information processing system according to claim  17 , wherein at least one of said processor bus, said memory bus, and said I/O bus is an address/data multiplexed type. 
     
     
       19. An information processing system according to claim  16 , wherein at least one of said processor bus, said memory bus, and said I/O bus is an address/data multiplexed type. 
     
     
       20. An information processing system comprising: 
       a processor bus, said processor bus for transferring data, address, and control signals;  
       a processor coupled to said processor bus;  
       a cache memory coupled to said processor bus through said processor;  
       a memory bus, said memory bus for transferring data, address, and control signals;  
       a main memory coupled to said memory bus;  
       an I/O bus, said I/O bus for transferring data, address, and control signals; and  
       a display control device coupled to said I/O bus;  
       wherein said information processing system enables a transfer of data between any arbitrary two of said processor, said main memory and said display control device via corresponding two of said processor bus, said memory bus and said I/O bus.  
     
     
       21. An information processing system according to claim  20 , wherein 
       each of said processor bus, said memory bus, and said I/O bus has a data bus for transferring said data, an address bus for transferring said address, and a control bus for transferring said control signals.  
     
     
       22. An information processing system according to claim  21 , wherein at least one of said processor bus, said memory bus, and said I/O bus is an address/data multiplexed type. 
     
     
       23. An information processing system according to claim  20 , wherein at least one of said processor bus, said memory bus, and said I/O bus is an address/data multiplexed type. 
     
     
       24. An information processing system comprising: 
       a processor;  
       a cache memory directly coupled to said processor;  
       a processor bus coupled to said processor for transferring data, address, and control signals;  
       a main memory;  
       a memory bus coupled to said main memory for transferring data, address, and control signals;  
       a file controller for controlling disk files; and  
       a system bus coupled to said file controller for transferring data, address, and control signals;  
       wherein said information processing system enables a transfer of data between any arbitrary two of said processor, said main memory and said file controller via corresponding two of said processor bus, said memory bus and said system bus.  
     
     
       25. An information processing system according to claim  24 , wherein at least one of said processor bus, said memory bus and said system bus is an address/data multiplexed type. 
     
     
       26. An information processing system according to claim  24 , wherein 
       each of said processor bus, said memory bus, and said system bus has a data bus for transferring said data, an address bus transferring said address, and a control bus for transferring said control signals.  
     
     
       27. An information processing system comprising: 
       a processor;  
       a cache memory directly coupled to said processor;  
       a processor bus coupled to said processor for transferring data, address, and control signals;  
       a main memory;  
       a memory bus coupled to said main memory for transferring data, address, and control signals;  
       two I/O devices; and  
       an I/O bus coupled to said two I/O devices, said I/O bus for transferring data, address, and control signals;  
       wherein said information processing system enables a transfer of data between any arbitrary two of said processor, said main memory and one of said two I/O devices via corresponding two of said processor bus, said memory bus and said I/O bus.  
     
     
       28. An information processing system according to claim  27 , wherein one of said I/O devices is a controller for displaying images. 
     
     
       29. An information processing system comprising: 
       a processor bus, said processor bus for transferring address, and control signals;  
       a processor;  
       a cache memory coupled to said processor bus through said processor;  
       a main memory;  
       a memory bus coupled to said main memory for transferring data, address and control signals;  
       two devices; and  
       a system bus coupled to said two devices, said system bus for transferring data, address, and control signals;  
       wherein said information processing system enables a transfer of data between any arbitrary two of said processor, said main memory and one of said two I/O devices via corresponding two of said processor bus, said memory bus and said system bus.  
     
     
       30. An information processing system according to claim  29 , wherein one of said devices is a controller for displaying images.