US6198379B1ExpiredUtility

Semiconductor component with piezoresistive measuring shunts

28
Assignee: BOSCH GMBH ROBERTPriority: Jun 19, 1997Filed: Jun 11, 1998Granted: Mar 6, 2001
Est. expiryJun 19, 2017(expired)· nominal 20-yr term from priority
Inventors:Oliver Schatz
G01L 9/0055
28
PatentIndex Score
0
Cited by
10
References
10
Claims

Abstract

A circuit arrangement implemented as an integrated semiconductor component has a measured value acquisition circuit that can be connected to an analysis circuit, in particular a piezoresistive measuring bridge containing piezoresistive measuring shunts diffused on a semiconductor substrate. The piezoresistive measuring shunts are connected to metallic terminal contacts by diffused terminal resistors having a negligible piezoresistive resistance. To avoid terminal-related offset errors on the measuring shunts in particular, the terminal resistors are designed as identical, elongated, generally curved area structures that taper toward the front end and are connected to a measuring shunt on the front end and to a metallic terminal contact on the opposite end.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A circuit arrangement implemented as an integrated semiconductor component and having a measured value acquisition circuit connectable to an analysis circuit, the circuit arrangement comprising: 
       piezoresistive measuring shunts diffused on a semiconductor substrate, the analysis circuit including the piezoresistive measuring shunts;  
       diffused terminal resistors having a negligible piezoresistive resistance, the diffused terminal resistors including identical, elongated, curved structures; and  
       metallic terminal contacts connected to the piezoresistive measuring shunts by the diffused terminal resistors,  
       wherein each of the curved structures has a first end for coupling to one of the piezoresistive measuring shunts and a second end, opposite the first end, for coupling to one of the metallic terminal contacts, each of the curved structures tapering toward the first end, and  
       wherein the first end expands from the taper to a rectangular or square shape.  
     
     
       2. The circuit arrangement according to claim  1 , 
       wherein each of the diffused terminal resistors includes:  
       a base body including a first area for connecting to the metallic terminal contacts,  
       a head portion having one of a rotational symmetry and a mirror symmetry and positioned at a predetermined distance from the base body, the head portion including a second area for connecting to the piezoresistive measuring shunts, the second area being smaller than the first area, and  
       a neck portion coupling the base body to the head portion, the neck portion having a cross section increasing from the head portion to the base body,  
       wherein the metallic terminal contacts are positioned at a location of the base body, the location being positioned at a maximum distance away from the head portion.  
     
     
       3. The circuit arrangement according to claim  2 , wherein the base body has a rectangular shape and has a narrow side adjacent to the neck portion. 
     
     
       4. The circuit arrangement according to claim  2 , wherein the neck portion has a curved shape. 
     
     
       5. The circuit arrangement according to claim  1 , wherein two of the diffused terminal resistors are arranged in a pair and in a side-by-side manner on at least one of the piezoresistive measuring shunts. 
     
     
       6. The circuit arrangement according to claim  1 , wherein the diffused terminal resistors are covered with a layer having a first doping, the piezoresistive measuring shunts having a second doping, the first doping substantially corresponding to the second doping. 
     
     
       7. The circuit arrangement according to claim  1 , wherein the diffused terminal resistors are formed in a highly-doped, low-resistance diffusion level. 
     
     
       8. The circuit arrangement according to claim  1 , wherein the analysis circuit includes a piezoresistive measuring bridge. 
     
     
       9. A circuit arrangement implemented as an integrated semiconductor component and having a measured value acquisition circuit connectable to an analysis circuit, the circuit arrangement comprising: 
       piezoresistive measuring shunts diffused on a semiconductor substrate, the analysis circuit including the piezoresistive measuring shunts;  
       diffused terminal resistors having a negligible piezoresistive resistance, the diffused terminal resistors including identical, elongated, curved structures; and  
       metallic terminal contacts connected to the piezoresistive measuring shunts by the diffused terminal resistors,  
       wherein each of the curved structures has a first end for coupling to one of the piezoresistive measuring shunts and a second end, opposite the first end, for coupling to one of the metallic terminal contacts, each of the curved structures tapering toward the first end  
       wherein each of the diffused terminal resistors includes:  
       a base body including a first area for connecting to the metallic terminal contacts,  
       a head portion having one of a rotational symmetry and a mirror symmetry and positioned at a predetermined distance from the base body, the head portion including a second area for connecting to the piezoresistive measuring shunts, the second area being smaller than the first area, and  
       a neck portion coupling the base body to the head portion, the neck portion having a cross section increasing from the head portion to the base body,  
       wherein the metallic terminal contacts are positioned at a location of the base body, the location being positioned at a maximum distance away from the head portion,  
       wherein the head portion has a square shape, and  
       wherein the head portion includes chamfered corners connecting to at least one of the piezoresistive measuring shunts.  
     
     
       10. A circuit arrangement implemented as an integrated semiconductor component and having a measured value acquisition circuit connectable to an analysis circuit, the circuit arrangement comprising: 
       piezoresistive measuring shunts diffused on a semiconductor substrate, the analysis circuit including the piezoresistive measuring shunts;  
       diffused terminal resistors having a negligible piezoresistive resistance, the diffused terminal resistors including identical, elongated, curved structures; and  
       metallic terminal contacts connected to the piezoresistive measuring shunts by the diffused terminal resistors,  
       wherein each of the curved structures has a first end for coupling to one of the piezoresistive measuring shunts and a second end, opposite the first end, for coupling to one of the metallic terminal contacts, each of the curved structures tapering toward the first end  
       wherein each of the diffused terminal resistors includes:  
       a base body including a first area for connecting to the metallic terminal contacts,  
       a head portion having one of a rotational symmetry and a mirror symmetry and positioned at a predetermined distance from the base body, the head portion including a second area for connecting to the piezoresistive measuring shunts, the second area being smaller than the first area, and  
       a neck portion coupling the base body to the head portion, the neck portion having a cross section increasing from the head portion to the base body,  
       wherein the metallic terminal contacts are positioned at a location of the base body, the location being positioned at a maximum distance away from the head portion, and  
       wherein the head portion expands from the taper to a square or rectangular shape.

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