Formation of out-diffused bitline by laser anneal

Abstract

The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused bitline can also be formed utilizing an ion implantation step.

Having thus described our invention, what we claim as new, and desire to secure by the letters patent is:  
     
       1. A method of forming a bitline buried below the transfer gate of a vertical semiconductor memory cell, said method comprising the steps of: 
       (a) forming at least one trench region in a semiconductor substrate;  
       (b) forming a conformal layer in said at least one trench region and on exposed surfaces of said semiconductor substrate, wherein said conformal layer comprises a dopant source material which comprises a dopant carrying material and a dopant element which is capable of being released upon exposure to laser light;  
       (c) depositing a recessable material on the structure provided in step (b);  
       (d) recessing some, but not all, of said recessable material and said dopant source material leaving a masked region of said recessable material on a layer of said dopant source material in said at least one trench region;  
       (e) stripping the recessable material from said trench;  
       (f) laser annealing the structure provided in step (e) to out-diffuse the dopant element from the recessed dopant source material into said semiconductor substrate;  
       (g) stripping any remaining recessed source material from said at least one trench region; and  
       (h) etching the out-diffused region under conditions effective to form a buried bitline in said semiconductor substrate.  
     
     
       2. The method of claim  1  wherein said semiconductor substrate is composed of Si, Ge, SiGe, GaAs, GaP, InAs or InP. 
     
     
       3. The method of claim  2  wherein said semiconductor substrate is Si. 
     
     
       4. The method of claim  2  wherein said semiconductor substrate is doped with a p-type dopant or a n-type dopant. 
     
     
       5. The method of claim  1  wherein said dopant carrying material is composed of polysilicon, a polysilicide, a polysilane or a polysiloxane. 
     
     
       6. The method of claim  5  wherein said dopant carrying material is polysilicon. 
     
     
       7. The method of claim  1  wherein said dopant element is a n-type dopant element or a p-type dopant element. 
     
     
       8. The method of claim  7  wherein said n-type dopant element is As, P or Sb. 
     
     
       9. The method of claim  7  wherein said p-type dopant element is B, Ga or In. 
     
     
       10. The method of claim  1  wherein said conformal layer is deposited by chemical vapor deposition (CVD), plasma vapor deposition (PVD) or enhanced PVD. 
     
     
       11. The method of claim  1  wherein said recessing step is carried out utilizing an isotropic etching process or an acid diffusion process. 
     
     
       12. The method of claim  1  wherein said laser annealing step is carried out in an inert gas atmosphere, oxygen or mixtures thereof. 
     
     
       13. The method of claim  12  wherein said laser annealing step is carried out in oxygen. 
     
     
       14. The method of claim  1  wherein said laser annealing step is carried out with a laser source that is capable of emitting light having a wavelength of from about 100 to about 450 nm and an energy of from about 10 to about 2000 eV. 
     
     
       15. The method of claim  14  wherein said laser annealing step is carried out with a laser source that is capable of emitting light having a wavelength of from about 248 to about 308 nm and an energy of from about 100 to about 400 eV. 
     
     
       16. The method of claim  1  wherein said laser annealing step is a multiple pulse step which is carried out at a temperature of from about 500° to about 1400° C. for a time period of from about 10 nanoseconds to about 10 milliseconds. 
     
     
       17. The method of claim  16  wherein said laser annealing step is carried out at a temperature of from about 950° to about 1350° C. for a time period of from about 100 nanoseconds to about 1 millisecond. 
     
     
       18. The method of claim  1  wherein said laser annealing step is carried out by blanket exposure or by a mask and trim step. 
     
     
       19. The method of claim  1  wherein said stripping step, step (g), includes the use of a wet chemical etchant. 
     
     
       20. The method of claim  1  wherein step (h) is conducted using an anisotropic etching process selected from the group consisting of reactive ion etching and plasma etching. 
     
     
       21. The method of claim  1  wherein said laser annealing step is carried out by blanket exposure or by a mask and trim step.