US6208168B1ExpiredUtility

Output driver circuits having programmable pull-up and pull-down capability for driving variable loads

94
Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Jun 27, 1997Filed: Jun 26, 1998Granted: Mar 27, 2001
Est. expiryJun 27, 2017(expired)· nominal 20-yr term from priority
Inventors:Sang-Jae Rhee
G11C 7/1069G11C 7/1057H03K 19/018585H03K 19/0005G11C 7/1051
94
PatentIndex Score
127
Cited by
20
References
5
Claims

Abstract

Output drivers preferably contain a plurality of driver circuits therein that are commonly connected to an output line to be driven and can be selectively enabled or disabled to increase or decrease drive capability, respectively. Driver circuits may include first and second control signal lines (e.g., MRS 1, MRS 2 ), a first pull-up/pull-down driver circuit having first and second data inputs, a first control input electrically coupled to the first control signal line (e.g., MRS 1 ) and a second control input, and a second pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit, respectively, a first control input electrically coupled to the second control signal line (e.g., MRS 2 ) and a second control input. First and second complementary control signals lines (e.g., {overscore (MRS 1 +L )}, {overscore (MRS 2 +L )}) are also preferably provided and the second control inputs of the first pull-up/pull-down driver circuit and second pull-up/pull-down driver circuit are electrically coupled to the first and second complementary control signal lines, respectively. These control signal lines and complementary control signal lines can be used to control the number of driver circuits that are active within the output driver, based on loading conditions.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A programmable output driver circuit, comprising: 
       a control signal generator that generates a first control signal on a first control signal line and a second control signal on a second control signal line, in response to a mode control signal and an address;  
       a first pull-up/pull-down driver circuit, said first pull-up/pull-down driver circuit having a data input, a control signal input responsive to the first control signal and an output;  
       a second pull-up/pull-down driver circuit, said second pull-up/pull-down driver circuit having a data input electrically coupled to the data input of said first pull-up/pull-down driver circuit, a control signal input responsive to the second control signal and an output electrically coupled to the output of said first pull-up/pull-down driver circuit; and  
       a mode register set controller that generates the mode control signal in response to a plurality of command signals;  
       wherein said control signal generator comprises a plurality of devices having first inputs that receive the mode control signal and second inputs that receive the address, wherein said control signal generator also generates complementary versions of the first and second control signals; wherein said first pull-up/pull-down driver circuit is responsive to the complementary version of the first control signal; and wherein said second pull-up/pull-down driver circuit is responsive to the complementary version of the second control signal.  
     
     
       2. The driver circuit of claim  1 , wherein the first and second control signals are disabled when the mode control signal is inactive; and wherein the first and second control signals match the address when the mode control signal is active. 
     
     
       3. The driver circuit of claim  1 , further comprising a third pull-up/pull-down driver circuit having a data input electrically coupled to the data input of said first pull-up/pull-down driver circuit. 
     
     
       4. The driver circuit of claim  3 , wherein said third pull-up/pull-down driver circuit is not responsive to signals generated by said control signal generator. 
     
     
       5. The driver circuit of claim  1 , wherein the first and second control signals are disabled when the mode control signal is inactive; and wherein the first and second control signals match the address when the mode control signal is active.

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