Input circuit

Abstract

An input circuit is provided with a gate with an input end thereof connected to an input terminal to which an external signal is input, the gate allows or prohibits the output of the external signal in accordance with a control signal. The input circuit also includes a latch circuit that holds the output from the gate and outputs the signal thus held to an internal input terminal. This structure prevents any inflow of a through current, and prevents erroneous operation of an internal circuit resulting from change in the signal level at the internal input terminal.

What is claimed is:  
     
       1. An input circuit connected between an input port and an output port, comprising: 
       a three-state inverter coupled to receive a control signal and connected to receive an input signal from the input port, said three-state inverter outputs a first signal as having a voltage level that is an inversion of a voltage level of the input signal when the control signal has a first voltage level and outputs the first signal as having a high impedance state when the control signal has a second voltage level,  
       said three-state inverter having at least first, second and third MOS transistors coupled in series, the first and second MOS transistors being a same electrical type, gate electrodes of the second and third MOS transistors being coupled to receive the input signal, and a gate electrode of the first MOS transistor being coupled to receive the control signal; and  
       a latch circuit coupled to said three-state inverter, said latch circuit provides an output signal to the output port, said latch circuit comprising  
       a logic circuit having first and second input terminals and an output terminal, the first input terminal being coupled to receive the first signal and the second input terminal being coupled to a reset signal, said logic circuit provides at the output terminal the output signal as having a voltage level that is an inversion of the voltage level of the first signal when a voltage level of the reset signal is a third voltage level and provides at the output terminal the output signal as having a predetermined voltage level when the voltage level of the reset signal is a fourth voltage level, and  
       an inverter having input and output terminals, the input terminal of said inverter being coupled to the output terminal of said logic circuit and the output terminal of said inverter being coupled to the first input terminal of said logic circuit.  
     
     
       2. The input circuit of claim  1 , wherein said logic circuit is a NAND gate. 
     
     
       3. The input circuit of claim  1 , wherein said three-state inverter further comprises a fourth MOS transistor coupled in series with the third MOS transistor, a gate electrode of the fourth MOS transistor being coupled to an inversion of the control signal. 
     
     
       4. The input circuit of claim  1 , wherein the reset signal and the control signal are independent of each other. 
     
     
       5. An input circuit connected between an input port and an output port, comprising: 
       a first transfer gate coupled to receive a control signal and connected to receive an input signal from the input port, said first transfer gate outputs a first signal as having a voltage level that is the same as a voltage level of the input signal when a voltage level of the control signal has a first voltage level and outputs the first signal as having a high impedance state when the voltage level of the control signal has a second voltage level; and  
       a latch circuit coupled to said first transfer gate, said latch circuit provides an output signal to the output port, said latch circuit comprising  
       a logic circuit having first and second input terminals and an output terminal, the first input terminal being coupled to receive the first signal and the second input terminal being coupled to receive a reset signal, said logic circuit provides at the output terminal a second signal as having a voltage level that is an inversion of the voltage level of the first signal when a voltage level of the reset signal is a third voltage level and provides at the output terminal the second signal as having a predetermined voltage level when the voltage level of the reset signal is a fourth voltage level,  
       an inverter having input and output terminals, the input terminal of said inverter being coupled to the output terminal of said logic circuit, said inverter provides at the output terminal of said inverter connected to the output port the output signal as having a voltage level that is an inversion of the voltage level of the second signal, and  
       a second transfer gate coupled to receive the control signal and connected between the output terminal of said inverter and the first input terminal of said logic circuit, said second transfer gate outputs to said logic circuit a third signal as having a voltage level that is the same as the voltage level of the output signal when the voltage level of the control signal has the second voltage level and outputs to said logic circuit the third signal as having a high impedance state when the voltage level of the control signal is the first voltage level.  
     
     
       6. The input circuit of claim  5 , wherein said logic circuit is a NOR gate. 
     
     
       7. The input circuit of claim  5 , wherein the reset signal and the control signal are independent of each other.