Method and system for asynchronous sample rate conversion using a noise-shaped numerically control oscillator

Abstract

Asynchronous sample rate conversion is performed using a noise-shaped numerically controlled oscillator (204,420) that generates a clock (207,428) that is synchronous to the system clock (217,424) but having a time average frequency that is equal to a multiple (X) of the asynchronous sample rate frequency required for the conversion. Unwanted spectral energy in the generated clock (207,428) is noise-shaped out of the pass-band and so does not degrade signal performance. For digital-to-analog conversion, the generated clock (207) is used to time an interpolation (206) of digital data (DATAFs) by an multiple X to produce an interpolated signal (DATAFsX) having a time average rate equal to the over-sampling frequency but being synchronized with the system clock (217). The interpolated signal (DATAFsX) is then converted (216) to an analog signal using a derivative of the system clock (217), or can be output as digital data at the rate derived from the system clock. For analog-to-digital conversion, the generated clock (428) clocks an analog-to-digital conversion (415) synchronous with the system clock but having a time average of the over-sampling frequency. It can be seen the present invention performs asynchronous sample rate conversion without the need for an analog PLL and with simplified circuitry such that no multipliers or DSP utilization is required.

What is claimed is:  
     
       1. A method for asynchronous sample rate conversion, comprising the steps of: 
       receiving data having a sample frequency, the sample frequency being asynchronous with a system clock signal having a system frequency;  
       interpolating the data to provide an oversampled information signal having a new frequency in response to a first clock signal, the new frequency having an average value and having substantially all phase noise removed from a frequency band of interest;  
       using a numerically controlled oscillator to generate the first clock signal, the numerically controlled oscillator receiving a numerical control signal and the system clock signal, the numerical control signal representing a difference in frequency between a first multiple of the system frequency and a second multiple of the sample frequency;  
       providing the first clock signal at an oversampling frequency which is synchronized to the system clock signal and having minimal frequency components associated with a predetermined base bandwidth of interest, the first clock signal having a significantly lower frequency than the system clock signal; and  
       processing the oversampled information signal by phase modulating with a sigma-delta modulator the data while maintaining substantially the same frequency content of the data within the predetermined base bandwidth of interest; and  
       decimating the data to provide the data at a predetermined output frequency synchronous to the system clock signal.  
     
     
       2. The method of claim  1  wherein the step of receiving data further comprises receiving a digital stream of data and the data is converted to an analog form after the step of decimating. 
     
     
       3. The method of claim  1  wherein the step of providing the first clock signal further comprises: 
       using a second sigma-delta modulator to provide a count signal which is a quantized number of system clock periods in a predetermined first clock signal period; and  
       counting cycles of the system clock signal in response to the count signal to provide the first signal therefrom, the steps of providing a count signal and counting cycles of the system clock signal removing substantially all phase noise associated with the first clock signal out of the predetermined base bandwidth of interest.  
     
     
       4. An asynchronous sample rate converter using a noise shaped numerically controlled oscillator, comprising: 
       a source of digital information for providing information at a sample rate;  
       an interpolator coupled to the source of digital information, the interpolator providing an oversampling information signal having a new rate in response to an oversampling clock, the new rate having an average value and having all phase noise removed from a frequency band of interest;  
       a numerically controlled oscillator coupled to the interpolator for providing the oversampling clock in response to a numerical control signal and a system clock, the numerical control signal representing a rate difference between the information at a sample rate and a multiple of the system clock;  
       a sigma delta modulator coupled to the interpolator for providing the information at a system clock rate which is interpolated from the new rate of the oversampling information signal; and  
       a decimator coupled to the sigma delta modulator, the decimator providing the information at a rate of a multiple of the system clock, where a divisor which determines the multiple of the system clock is a decimation rate;  
       the information provided by the decimator being suitable for further digital processing or D/A conversion at the rate which is the multiple of the system clock and synchronous to the system clock.  
     
     
       5. The asynchronous sample rate converter of claim  4  further comprising: 
       an oversampling converter coupled to an output of the decimator, the oversampling converter providing an analog representation of the source of digital information.  
     
     
       6. An asynchronous sample rate converter using a noise shaped numerically controlled oscillator, comprising: 
       an interpolator having an input for receiving a source of digital information having a sample rate, the interpolator providing an oversampled information signal having a new rate in response to an oversampled clock signal, the new rate having an average value and having all phase noise removed from a frequency band of interest;  
       a numerically controlled oscillator coupled to the interpolator for providing the oversampled clock signal in response to a numerical control signal and a system clock signal, the numerical control signal representing a rate difference between the sample rate of the digital information and a multiple of the system clock signal;  
       a sigma delta modulator coupled to the interpolator for providing the information at a system clock signal rate which is interpolated from the new rate of the oversampled information signal; and  
       a decimator coupled to the sigma delta modulator, the decimator providing the digital information at a rate which is a multiple of the system clock signal, where a divisor which determines the multiple of the system clock signal is a decimation rate;  
       the information provided by the decimator being suitable for further digital processing or digital-to-analog conversion.