S-R flip-flop circuit

Abstract

An S-R flip-flop circuit is provided using two stacks of gates 2, 6 with an internal signal Int stored therebetween. Feedback from the output O is used to switch the state of the internal signal Int in a manner that provides an edge-triggered response for at least one of the inputs.

What is claimed is:  
     
       1. An S-R flip-flop circuit comprising: 
       (i) a first signal input for receiving a first input signal having a signal value of either A or B;  
       (ii) a second signal input for receiving a second input signal having a signal value of either C or D;  
       (iii) an output signal node bearing an output signal having a signal value of either E or F;  
       (iv) an internal node bearing an internal signal having a signal value of either G or H;  
       (v) a first stack of gates responsive to said output signal and said first input signal; and  
       (vi) a second stack of gates responsive to said internal signal, said first input signal and said second input signal, said internal node being between said first stack of gates and said second stack of gates; wherein  
       (vii) said first stack of gates forces said internal signal to G when said first input signal is A and said output signal is E and said first stack of gates forces said internal signal to H when said first input signal is B and said output signal is F;  
       (viii) said second stack of gates forces said output signal to F when said internal signal is G and said first input signal is B, whereby  
       (ix) when said output signal is E and said first input signal is A, said internal signal will be G and a transition in said first signal from A to B will force said output signal to transition from E to F followed by said internal signal being forced to transition from G to H, thereby effecting an edge-triggered change in said output signal from E to F in response to said first input signal changing from A to B.  
     
     
       2. An S-R flip-flop circuit as claimed in claim  1 , comprising an internal signal level holding circuit for maintaining said internal signal at a signal value when said output node is undriven. 
     
     
       3. An S-R flip-flop circuit as claimed in claim  1 , comprising an output signal level holding circuit for maintaining said output signal at a signal value when said output node is undriven. 
     
     
       4. An S-R flip-flop circuit as claimed in claim  1 , wherein said second stack of gates is responsive to said second input signal to force said output signal to E when said second input signal is A independent of signals values of said internal signal or said first input signal. 
     
     
       5. An S-R flip-flop circuit as claimed in claim  1 , wherein said first input signal transitioning from A to B whilst said second input signal is C is forbidden. 
     
     
       6. An S-R flip-flop circuit as claimed in claim  1 , further comprising: 
       a further internal node bearing a further internal signal having a signal value of either I or J; and  
       a third stack of gates responsive to said output signal and said second input signal; wherein  
       said second stack of gates is also responsive to said further internal signal, said further internal node being between said first stack of gates and said second stack of gates;  
       said third stack of gates forces said further internal signal to I when said second input signal is C and said output signal is E and said third stack of gates forces said further internal signal to J when said second input signal is D and said output signal is F;  
       said second stack of gates forces said output signal to E when said further internal signal is J and said second input signal is C, whereby  
       when said output signal is F and said second input signal is D, said further internal signal will be J and a transition in said second signal from D to C will force said output signal to transition from F to E followed by said further internal signal being forced to transition from J to I, thereby effecting an edge-triggered change in said output signal from F to E in response to said second input signal changing from B to C.  
     
     
       7. An S-R flip-flop circuit as claimed in claim  6 , comprising a further internal signal level holding circuit for maintaining said further internal signal at a signal value when said further internal signal node is undriven. 
     
     
       8. An S-R flip-flop circuit as claimed in claim  1 , wherein said first stack of gates comprises a stack of field effect transistors arranged in series between a supply voltage source and a ground voltage source and each being switched by a respective one of said first input signal and said output signal. 
     
     
       9. An S-R flip-flop circuit as claimed in claim  8 , wherein said internal signal node is coupled to a midpoint of said first stack of gates. 
     
     
       10. An S-R flip-flop circuit as claimed in claim  1 , wherein said second stack of gates comprises a stack of field effect transistors arranged in series between a supply voltage source and a ground voltage source and each being switched by a respective one of said first input signal, said second input signal and said internal signal. 
     
     
       11. An S-R flip-flop circuit as claimed in claim  10 , wherein said output signal node is coupled to a midpoint of said second stack of gates. 
     
     
       12. An S-R flip-flop circuit as claimed in claim  6 , wherein said third stack of gates comprises a stack of field effect transistors arranged in series between a supply voltage source and a ground voltage source and each being switched by a respective one of said second input signal and said output signal. 
     
     
       13. An S-R flip-flop circuit as claimed in claim  12 , wherein said further internal signal node is coupled to a midpoint of said third stack of gates. 
     
     
       14. An S-R flip-flop circuit as claimed in claim  6 , wherein said second stack of gates comprises a stack of field effect transistors arranged in series between a supply voltage source and a ground voltage source and each being switched by a respective one of said first input signal, said second input signal, said internal signal and said further internal signal. 
     
     
       15. An S-R flip-flop circuit as claimed in claim  14 , wherein said output signal node is coupled to a midpoint of said second stack of gates. 
     
     
       16. An S-R flip-flop circuit as claimed in claim  1 , wherein A is a high signal level and B is a low signal level. 
     
     
       17. An S-R flip-flop circuit as claimed in claim  1 , wherein C is a high signal level and D is a low signal level. 
     
     
       18. An S-R flip-flop circuit as claimed in claim  1 , wherein E is a high signal level and F is a low signal level. 
     
     
       19. An S-R flip-flop circuit as claimed in claim  1 , wherein G is a low signal level and H is a high signal level. 
     
     
       20. An S-R flip-flop circuit as claimed in claim  6 , wherein I is a low signal level and J is a high signal level.