Active matrix display and image forming system

Abstract

A plurality of partial image display portions are provided. Each of the partial image display portions is formed by at least one signal line driver circuits and at least one of scanning line driver circuits. Each partial image display portion displays a part of one frame of image. The whole one frame of image is displayed by all of the partial image display portions.

What is claimed is:  
     
       1. An active matrix display device comprising: 
       a substrate having at least a first portion and a second portion separate from said first portion;  
       a display region having at least first and second sections, each of said sections provided with an active matrix circuit comprising a plurality of pixel electrodes arranged in a matrix form and a plurality of switching elements for switching said pixel electrodes, wherein said first section is formed over said first portion of the substrate and said second section is formed over said second portion of the substrate;  
       first and second signal line driver circuits operating to supply image signals to the active matrix circuit of the first and second sections, respectively;  
       wherein said first and second signal line driver circuits are located outside said display region, and are operated so that the active matrix circuits of the first and second sections are scanned or driven in an opposite direction from each other.  
     
     
       2. The active matrix display device according to claim  1  further comprising first and second FIFO memories corresponding to each of said active matrix circuits. 
     
     
       3. The active matrix display device according to claim  1  wherein each of said first and second signal line driver circuits comprises shift register and a sampling circuit, said sampling circuit sampling inputted image signals in response to outputs of said shift register and supplying the sampled signals into said signal lines. 
     
     
       4. An active matrix display device comprising: 
       a substrate having at least a first portion and a second portion separate from said first portion;  
       a display region having at least first and second sections defined on said substrate, each of said sections provided with an active matrix circuit comprising a plurality of pixel electrodes arranged in a matrix form and a plurality of switching elements for switching said pixel electrodes wherein said switching elements comprise thin film transistors formed over said substrate and wherein said first section is formed over said first portion of the substrate and said second section is formed over said second portion of the substrate;  
       first and second signal line driver circuits operating to supply image signals to the corresponding active matrix circuits, respectively, wherein said first and second signal line driver circuits comprise thin film transistors formed over said substrate;  
       wherein said signal line driver circuits are disposed on a peripheral portion of said substrate outside said display region, and are operated so that the active matrix circuits of the first and second sections are driven in an opposite direction from each other.  
     
     
       5. The active matrix display device according to claim  4  further comprising first and second FIFO memories corresponding to each of said active matrix circuits. 
     
     
       6. The active matrix display device according to claim  4  wherein each of said first and second signal line driver circuits comprises shift register and a sampling circuit, said sampling circuit sampling inputted image signals in response to outputs of said shift register and supplying the sampled signals into said signal lines. 
     
     
       7. An active matrix display device comprising: 
       a substrate having at least a first portion and a second portion separate from said first portion;  
       a display region constituted with at least first and second sections, each of said sections provided with an active matrix circuit comprising a plurality of pixel electrodes arranged in a matrix form and a plurality of switching elements for switching said pixel electrodes, wherein said first section is formed over said first portion of the substrate and said second section is formed over said second portion of the substrate;  
       first and second scanning line driver circuits for scanning the active matrix circuit of the first and second sections, respectively;  
       wherein said first and second scanning line driver circuits are located outside said display region, and are operated so that the active matrix circuits of the first and second sections are scanned in an opposite direction from each other.  
     
     
       8. The active matrix display device according claim  7  wherein said first and second scanning line driver are operated so that the active matrix circuits of the first and second sections are scanned in an opposite direction from each other. 
     
     
       9. The active matrix display device according to claim  7  further comprising first and second FIFO memories corresponding to each of said active matrix circuits. 
     
     
       10. The active matrix display device according to claim  7  wherein each of said first and second scanning line driver circuits comprises shift register and a sampling circuit, said sampling circuit sampling inputted image signals in response to outputs of said shift register and supplying the sampled signals into said signal lines. 
     
     
       11. An active matrix display device comprising: 
       a substrate having at least a first portion and a second portion separate from said first portion;  
       a display region constituted with at least first and second sections defined on said substrate, each of said sections provided with an active matrix circuit comprising a plurality of pixel electrodes arranged in a matrix form and a plurality of switching elements for switching said pixel electrodes wherein said switching elements comprise thin film transistors formed over said substrate and wherein said first section is formed over said first portion of the substrate and said second section is formed over said second portion of the substrate;  
       first and second scanning line driver circuits for scanning the active matrix circuits of the first and second sections, respectively, wherein said first and second signal line driver circuits comprise thin film transistors formed over said substrate;  
       wherein said scanning line driver circuits are disposed on a peripheral portion of said substrate outside said display region, and are operated so that the active matrix circuits of the first and second sections are scanned in an opposite direction from each other.  
     
     
       12. The active matrix display device according to claim  11  further comprising first and second FIFO memories corresponding to each of said active matrix circuits. 
     
     
       13. The active matrix display device according to claim  11  wherein each of said first and second scanning line driver circuits comprises shift register and a sampling circuit, said sampling circuit sampling inputted image signals in response to outputs of said shift register and supplying the sampled signals into said signal lines. 
     
     
       14. An active matrix display device comprising: 
       at least a first section, a second section, a third section and a fourth section;  
       said first section including:  
       a first plurality of pixel thin film transistors configured in a matrix form;  
       a first plurality of pixel electrodes each being connected to each of the first plurality of pixel thin film transistors;  
       a first plurality of source lines each being connected to a source region of each of the first plurality of pixel thin film transistors;  
       a first plurality of gate lines each being connected to a gate electrode of each of the first plurality of pixel thin film transistors;  
       a first source line driver circuit being connected to the first plurality of source lines;  
       a first gate line driver circuit being connected to the first plurality of gate lines;  
       wherein the first source line driver circuit is operated so that the first plurality of source lines are driven in a first driving direction;  
       wherein the first gate line driver circuit is operated so that the first plurality of gate lines are scanned in a first scanning direction,  
       said second section including:  
       a second plurality of pixel thin film transistors configured in a matrix form;  
       a second plurality of pixel electrodes each being connected to each of the second plurality of pixel thin film transistors;  
       a second plurality of source lines each being connected to a source region of each of the second plurality of pixel thin film transistors;  
       a second plurality of gate lines each being connected to a gate electrode of each of the second plurality of pixel thin film transistors;  
       a second source line driver circuit being connected to the second plurality of source lines;  
       a second gate line driver circuit being connected to the second plurality of gate lines;  
       wherein the second source line driver circuit is operated so that the second plurality of source lines are driven in a second driving direction;  
       wherein the second gate line driver circuit is operated so that the second plurality of gate lines are scanned in a second scanning direction;  
       said third section including:  
       a third plurality of pixel thin film transistors configured in a matrix form;  
       a third plurality of pixel electrodes each being connected to each of the third plurality of pixel thin film transistors;  
       a third plurality of source lines each being connected to a source region of each of the third plurality of pixel thin film transistors;  
       a third plurality of gate lines each being connected to a gate electrode of each of the third plurality of pixel thin film transistors;  
       a third source line driver circuit being connected to the third plurality of source lines;  
       a third gate line driver circuit being connected to the third plurality of gate lines;  
       wherein the third source line driver circuit is operated so that the third plurality of source lines are driven in a third driving direction;  
       wherein the third gate line driver circuit is operated so that the third plurality of gate lines are scanned in a third scanning direction;  
       said fourth section including:  
       a fourth plurality of pixel thin film transistors configured in a matrix form;  
       a fourth plurality of pixel electrodes each being connected to each of the fourth plurality of pixel thin film transistors;  
       a fourth plurality of source lines each being connected to a source region of each of the fourth plurality of pixel thin film transistors;  
       a fourth plurality of gate lines each being connected to a gate electrode of each of the fourth plurality of pixel thin film transistors;  
       a fourth source line driver circuit being connected to the fourth plurality of source lines;  
       a fourth gate line driver circuit being connected to the fourth plurality of gate lines;  
       wherein the fourth source line driver circuit is operated so that the fourth plurality of source lines are driven in a fourth driving direction;  
       wherein the fourth gate line driver circuit is operated so that the fourth plurality of gate lines are scanned in a fourth scanning direction,  
       wherein at least two of the first, second, third, and fourth driving directions are opposite from each other at a same time,  
       wherein at least two of the first, second, third and fourth scanning directions are opposite from each other at a same time.  
     
     
       15. A device according to claim  14  further comprising at least an FIFO memory corresponding to each of the first, second, third and fourth sections. 
     
     
       16. A device according to claim  14 , wherein each of the first, second, third and fourth source line driver circuits comprises a shift register and a sampling circuit, said sampling circuit sampling inputted image signals in response to outputs of the shift register and supplying the sampled signals into the first, second, third and fourth pluralities of source lines. 
     
     
       17. An active matrix display device comprising: 
       a substrate;  
       at least a first section, a second section, a third section and a fourth section;  
       said first section including:  
       a first plurality of pixel thin film transistors configured in a matrix form, each of the first plurality of pixel thin film transistors being formed over the substrate;  
       a first plurality of pixel electrodes each being connected to each of the first plurality of pixel thin film transistors;  
       a first plurality of source lines each being connected to a source region of each of the first plurality of pixel thin film transistors;  
       a first plurality of gate lines each being connected to a gate electrode of each of the first plurality of pixel thin film transistors;  
       a first source line driver circuit being connected to the first plurality of source lines;  
       a first gate line driver circuit being connected to the first plurality of gate lines;  
       wherein the first source line driver circuit is operated so that the first plurality of source lines are driven in a first driving direction;  
       wherein the first gate line driver circuit is operated so that the first plurality of gate lines are scanned in a first scanning direction,  
       said second section including:  
       a second plurality of pixel thin film transistors configured in a matrix form, each of the second plurality of pixel thin film transistors being formed over the substrate;  
       a second plurality of pixel electrodes each being connected to each of the second plurality of pixel thin film transistors;  
       a second plurality of source lines each being connected to a source region of each of the second plurality of pixel thin film transistors;  
       a second plurality of gate lines each being connected to a gate electrode of each of the second plurality of pixel thin film transistors;  
       a second source line driver circuit being connected to the second plurality of source lines;  
       a second gate line driver circuit being connected to the second plurality of gate lines;  
       wherein the second source line driver circuit is operated so that the second plurality of source lines are driven in a second driving direction;  
       wherein the second gate line driver circuit is operated so that the second plurality of gate lines are scanned in a second scanning direction;  
       said third section including:  
       a third plurality of pixel thin film transistors configured in a matrix form, each of the third plurality of pixel thin film transistors being formed over the substrate;  
       a third plurality of pixel electrodes each being connected to each of the third plurality of pixel thin film transistors;  
       a third plurality of source lines each being connected to a source region of each of the third plurality of pixel thin film transistors;  
       a third plurality of gate lines each being connected to a gate electrode of each of the third plurality of pixel thin film transistors;  
       a third source line driver circuit being connected to the third plurality of source lines;  
       a third gate line driver circuit being connected to the third plurality of gate lines;  
       wherein the third source line driver circuit is operated so that the third plurality of source lines are driven in a third driving direction;  
       wherein the third gate line driver circuit is operated so that the third plurality of gate lines are scanned in a third scanning direction;  
       said fourth section including:  
       a fourth plurality of pixel thin film transistors configured in a matrix form, each of the fourth plurality of pixel thin film transistors being formed over the substrate;  
       a fourth plurality of pixel electrodes each being connected to each of the fourth plurality of pixel thin film transistors;  
       a fourth plurality of source lines each being connected to a source region of each of the fourth plurality of pixel thin film transistors;  
       a fourth plurality of gate lines each being connected to a gate electrode of each of the fourth plurality of pixel thin film transistors;  
       a fourth source line driver circuit being connected to the fourth plurality of source lines;  
       a fourth gate line driver circuit being connected to the fourth plurality of gate lines;  
       wherein the fourth source line driver circuit is operated so that the fourth plurality of source lines are driven in a fourth driving direction;  
       wherein the fourth gate line driver circuit is operated so that the fourth plurality of gate lines are scanned in a fourth scanning direction,  
       wherein at least two of the first, second, third and fourth driving directions are opposite from each other at a same time,  
       wherein at least two of the first, second, third and fourth scanning directions are opposite from each other at a same time.  
     
     
       18. A device according to claim  17  further comprising at least an FIFO memory corresponding to each of the first, second, third and fourth sections. 
     
     
       19. A device according to claim  17 , wherein each of the first, second, third and fourth source line driver circuits comprises a shift register and a sampling circuit, said sampling circuit sampling inputted image signals in response to outputs of the shift register and supplying the sampled signals into the first, second, third and fourth pluralities of source lines. 
     
     
       20. An active matrix display device comprising: 
       at least a first section, a second section, a third section and a fourth section;  
       said first section including:  
       a first plurality of pixel thin film transistors configured in a matrix form;  
       a first plurality of pixel electrodes each being connected to each of the first plurality of pixel thin film transistors;  
       a first plurality of source lines each being connected to a source region of each of the first plurality of pixel thin film transistors;  
       a first plurality of gate lines each being connected to a gate electrode of each of the first plurality of pixel thin film transistors;  
       a first source line driver circuit being connected to the first plurality of source lines, said first source line driver circuit including a first plurality of source line driver thin film transistor;  
       a first gate line driver circuit being connected to the first plurality of gate lines, said first gate line driver circuit including a first plurality of gate line driver thin film transistor;  
       wherein the first source line driver circuit is operated so that the first plurality of source lines are driven in a first driving direction;  
       wherein the first gate line driver circuit is operated so that the first plurality of gate lines are scanned in a first scanning direction,  
       said second section including:  
       a second plurality of pixel thin film transistors configured in a matrix form;  
       a second plurality of pixel electrodes each being connected to each of the second plurality of pixel thin film transistors;  
       a second plurality of source lines each being connected to a source region of each of the second plurality of pixel thin film transistors;  
       a second plurality of gate lines each being connected to a gate electrode of each of the second plurality of pixel thin film transistors;  
       a second source line driver circuit being connected to the second plurality of source lines, said second source line driver circuit including a second plurality of source line driver thin film transistor;  
       a second gate line driver circuit being connected to the second plurality of gate lines, said second gate line driver circuit including a second plurality of gate line driver thin film transistor;  
       wherein the second source line driver circuit is operated so that the second plurality of source lines are driven in a second driving direction;  
       wherein the second gate line driver circuit is operated so that the second plurality of gate lines are scanned in a second scanning direction;  
       said third section including:  
       a third plurality of pixel thin film transistors configured in a matrix form;  
       a third plurality of pixel electrodes each being connected to each of the third plurality of pixel thin film transistors;  
       a third plurality of source lines each being connected to a source region of each of the third plurality of pixel thin film transistors;  
       a third plurality of gate lines each being connected to a gate electrode of each of the third plurality of pixel thin film transistors;  
       a third source line driver circuit being connected to the third plurality of source lines, said third source line driver circuit including a third plurality of source line driver thin film transistor;  
       a third gate line driver circuit being connected to the third plurality of gate lines, said third gate line driver circuit including a third plurality of gate line driver thin film transistor;  
       wherein the third source line driver circuit is operated so that the third plurality of source lines are driven in a third driving direction;  
       wherein the third gate line driver circuit is operated so that the third plurality of gate lines are scanned in a third scanning direction;  
       said fourth section including:  
       a fourth plurality of pixel thin film transistors configured in a matrix form;  
       a fourth plurality of pixel electrodes each being connected to each of the fourth plurality of pixel thin film transistors;  
       a fourth plurality of source lines each being connected to a source region of each of the fourth plurality of pixel thin film transistors;  
       a fourth plurality of gate lines each being connected to a gate electrode of each of the fourth plurality of pixel thin film transistors;  
       a fourth source line driver circuit being connected to the fourth plurality of source lines, said fourth source line driver circuit including a fourth plurality of source line driver thin film transistor;  
       a fourth gate line driver circuit being connected to the fourth plurality of gate lines, said fourth gate line driver circuit including a fourth plurality of gate line driver thin film transistor;  
       wherein the fourth source line driver circuit is operated so that the fourth plurality of source lines are driven in a fourth driving direction;  
       wherein the fourth gate line driver circuit is operated so that the fourth plurality of gate lines are scanned in a fourth scanning direction,  
       wherein at least two of the first, second, third and fourth driving directions are opposite from each other at a same time,  
       wherein at least two of the first, second, third and fourth scanning directions are opposite from each other at a same time.  
     
     
       21. A device according to claim  20  further comprising at least an FIFO memory corresponding to each of the first, second, third and fourth sections. 
     
     
       22. A device according to claim  20 , wherein each of the first, second, third and fourth source line driver circuits comprises a shift register and a sampling circuit, said sampling circuit sampling inputted image signals in response to outputs of the shift register and supplying the sampled signals into the first, second, third and fourth pluralities of source lines. 
     
     
       23. A device according to claim  20 , wherein each of the first, second, third and fourth pluralities of source and gate line driver circuit thin film transistors is one selected from the group consisting of a p-type thin film transistor, an n-type thin film transistor and a complementary thin film transistor. 
     
     
       24. An active matrix display device comprising: 
       a substrate;  
       at least a first section, a second section, a third section and a fourth section;  
       said first section including:  
       a first plurality of pixel thin film transistors configured in a matrix form, each of the first plurality of pixel thin film transistors being formed over the substrate;  
       a first plurality of pixel electrodes each being connected to each of the first plurality of pixel thin film transistors;  
       a first plurality of source lines each being connected to a source region of each of the first plurality of pixel thin film transistors;  
       a first plurality of gate lines each being connected to a gate electrode of each of the first plurality of pixel thin film transistors;  
       a first source line driver circuit being connected to the first plurality of source lines, said first source line driver circuit including a first plurality of source line driver thin film transistor, wherein each of the first plurality of source line driver thin film transistors is formed over the substrate;  
       a first gate line driver circuit being connected to the first plurality of gate lines, said first gate line driver circuit including a first plurality of gate line driver thin film transistor, wherein each of the first plurality of gate line driver thin film transistors is formed over the substrate;  
       wherein the first source line driver circuit is operated so that the first plurality of source lines are driven in a first driving direction;  
       wherein the first gate line driver circuit is operated so that the first plurality of gate lines are scanned in a first scanning direction,  
       said second section including:  
       a second plurality of pixel thin film transistors configured in a matrix form, each of the second plurality of pixel thin film transistors being formed over the substrate;  
       a second plurality of pixel electrodes each being connected to each of the second plurality of pixel thin film transistors;  
       a second plurality of source lines each being connected to a source region of each of the second plurality of pixel thin film transistors;  
       a second plurality of gate lines each being connected to a gate electrode of each of the second plurality of pixel thin film transistors;  
       a second source line driver circuit being connected to the second plurality of source lines, said second source line driver circuit including a second plurality of source line driver thin film transistor, wherein each of the second plurality of source line driver thin film transistors is formed over the substrate;  
       a second gate line driver circuit being connected to the second plurality of gate lines, said second gate line driver circuit including a second plurality of gate line driver thin film transistor, wherein each of the second plurality of gate line driver thin film transistors is formed over the substrate;  
       wherein the second source line driver circuit is operated so that the second plurality of source lines are driven in a second driving direction;  
       wherein the second gate line driver circuit is operated so that the second plurality of gate lines are scanned in a second scanning direction;  
       said third section including:  
       a third plurality of pixel thin film transistors configured in a matrix form, each of the third plurality of pixel thin film transistors being formed over the substrate;  
       a third plurality of pixel electrodes each being connected to each of the third plurality of pixel thin film transistors;  
       a third plurality of source lines each being connected to a source region of each of the third plurality of pixel thin film transistors;  
       a third plurality of gate lines each being connected to a gate electrode of each of the third plurality of pixel thin film transistors;  
       a third source line driver circuit being connected to the third plurality of source lines, said third source line driver circuit including a third plurality of source line driver thin film transistor, wherein each of the third plurality of source line driver thin film transistors is formed over the substrate;  
       a third gate line driver circuit being connected to the third plurality of gate lines, said third gate line driver circuit including a third plurality of gate line driver thin film transistor, wherein each of the third plurality of gate line driver thin film transistors is formed over the substrate;  
       wherein the third source line driver circuit is operated so that the third plurality of source lines are driven in a third driving direction;  
       wherein the third gate line driver circuit is operated so that the third plurality of gate lines are scanned in a third scanning direction;  
       said fourth section including:  
       a fourth plurality of pixel thin film transistors configured in a matrix form, each of the fourth plurality of pixel thin film transistors being formed over the substrate;  
       a fourth plurality of pixel electrodes each being connected to each of the fourth plurality of pixel thin film transistors;  
       a fourth plurality of source lines each being connected to a source region of each of the fourth plurality of pixel thin film transistors;  
       a fourth plurality of gate lines each being connected to a gate electrode of each of the fourth plurality of pixel thin film transistors;  
       a fourth source line driver circuit being connected to the fourth plurality of source lines, said fourth source line driver circuit including a fourth plurality of source line driver thin film transistor, wherein each of the fourth plurality of source line driver thin film transistors is formed over the substrate;  
       a fourth gate line driver circuit being connected to the fourth plurality of gate lines, said fourth gate line driver circuit including a fourth plurality of gate line driver thin film transistor, wherein each of the fourth plurality of gate line driver thin film transistors is formed over the substrate;  
       wherein the fourth source line driver circuit is operated so that the fourth plurality of source lines are driven in a fourth driving direction;  
       wherein the fourth gate line driver circuit is operated so that the fourth plurality of gate lines are scanned in a fourth scanning direction,  
       wherein at least two of the first, second, third and fourth driving directions are opposite from each other,  
       wherein at least two of the first, second, third and fourth scanning directions are opposite from each other at a same time.  
     
     
       25. A device according to claim  24  further comprising at least an FIFO memory corresponding to each of the first, second, third and fourth sections. 
     
     
       26. A device according to claim  24 , wherein each of the first, second, third and fourth source line driver circuits comprises a shift register and a sampling circuit, said sampling circuit sampling inputted image signals in response to outputs of the shift register and supplying the sampled signals into the first, second, third and fourth pluralities of source lines. 
     
     
       27. A device according to claim  24 , wherein each of the first, second, third and fourth pluralities of source and gate line driver circuit thin film transistors is one selected from the group consisting of a p-type thin film transistor, an n-type thin film transistor and a complementary thin film transistor.