D/A converter with a gamma correction circuit

Abstract

A D/A converter with a Gamma correction circuit according to the invention is designed for C-DAC which utilizes multiplexers to obtain reference voltages. This D/A converter takes up much less space and has more simple structure than the conventional R-DAC and 2-divided C-DAC. Therefore, this D/A converter has advantages of simple design and low cost. Furthermore, users can freely define the shape of a Gamma correction conversion curve to thereby widen application areas by adjusting terminal voltages.

What is claimed is:  
     
       1. A D/A converter with a Gamma correction circuit for receiving N-bit digital data and then outputting a corresponding analog output voltage, comprising: 
       a plurality of terminal voltage sources;  
       a first terminal voltage selector for obtaining a first reference voltage from said terminal voltage sources according to the k highest bits of said N-bit digital data;  
       a second terminal voltage selector for obtaining a second reference voltage from said terminal voltage sources according to the k highest bits of said N-bit digital data;  
       a voltage selector for obtaining a voltage difference between said first reference voltage and said second reference voltage according to the N−k lowest bits of said N-bit digital data;  
       a first switch, a second switch and a third switch connected to each other in series and coupled between said voltage selector and said second reference voltage;  
       a first capacitor connected in parallel across said voltage selector and charged by said voltage difference while said first switch is turned on; and  
       a second capacitor connected in parallel across said first capacitor and the charges of said first capacitor and said second capacitor are re-distributed to obtain said analog output voltage while said first switch and said third switch are turned off and said second switch is turned on.  
     
     
       2. A D/A converter as claimed in claim  1 , where is the capacitor of said first capacitor and said second capacitor are the same. 
     
     
       3. A D/A converter as claimed in claim  1 , wherein said second capacitor is reset while said first switch and said third switch are turned on. 
     
     
       4. A D/A converter as claimed in claim  1 , wherein said first terminal voltage selector and said second terminal voltage selector can be a multiplexer. 
     
     
       5. A D/A converter as claimed in claim  1 , wherein said voltage selector further includes: 
       an inverter, which receives the N−k lowest bits of said N-bit digital data in ascending order;  
       a first selecting switch for obtaining said first reference voltage according to the N−k lowest bits of said N-bit digital data; and  
       a second selecting switch for obtaining said second reference voltage according to the N−k lowest bits of said N-bit digital data which is outputted from said inverter.  
     
     
       6. A D/A converter as claimed in claim  1 , wherein the operations of said first switch through said third switch are as follows: 
       (a) said first switch and said third switch are turned on while said second switch is turned off according to the first bit of the N−k lowest bits of said N-bit digital data, thereby charging said first capacitor and resetting said second capacitor;  
       (b) turn off said first switch and said third switch while turn on said second switch after said first capacitor is fully charged, thereby re-distributing the charges stored in said first capacitor and said second capacitor;  
       (c) input the next bit of the N−k lowest bits of said N-bit digital data into said voltage selector and turn on said first switch while said second switch and said third switch are turned off, thereby charging said first capacitor again; and  
       (d) repeat (b) and (c) until the input of the N−k lowest bits of said N-bit digital data into said voltage selector is completed, thereby obtaining said analog output voltage corresponding to said N-bit digital data.  
     
     
       7. A D/A converter as claimed in claim  1 , wherein the number of said terminal voltage sources is 2 k +1. 
     
     
       8. A D/A converter as claimed in claim  1 , wherein said terminal voltage sources further divided into two groups of terminal voltage sources, V 2     k   ˜V 1  and V 2     k     −1 ˜V 0 . 
     
     
       9. A D/A converter as claimed in claim  1 , wherein said first terminal voltage selector for obtaining said first reference voltage from said group of terminal voltage sources of V 2     k   ˜V 1  according to the highest k bits of said N-bit digital data. 
     
     
       10. A D/A converter as claimed in claim  1 , wherein said second terminal voltage selector for obtaining said second reference voltage from said group of terminal voltage sources of V 2     k     −1 ˜V 0  according to the highest k bits of said N-bit digital data.