Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices

Abstract

A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices or master devices that are designed to run master cycles on the expansion bus. The master devices couple to the expansion bus through a common expansion master interface, which executes master cycles on the expansion bus on behalf of the master devices. The South bridge also includes an internal modular master expansion bus coupling the internal master devices to the common master interface. The internal modular master expansion bus permits the master devices to run master cycles to any expansion bus by understanding a standardized group of signals represented by the internal modular master expansion (IMAX) bus. The master interface then is responsible for understanding the protocol of the expansion bus and converting the IMAX master bus signals to signals compatible with the expansion bus. In addition, a dedicated target IMAX bus may also be provided for coupling internal targets within the South bridge to masters on the expansion bus through a common expansion target interface.

We claim:  
     
       1. A computer system, comprising: 
       a CPU;  
       a main memory;  
       at least one peripheral device coupled to said CPU and said memory by an expansion bus;  
       a bridge logic device connected to said expansion bus, said bridge logic being capable of running master cycles on said expansion bus;  
       wherein said bridge logic includes:  
       a plurality of master devices;  
       a common expansion bus master interface coupled to said expansion bus and to said plurality of master devices for executing expansion bus master cycles on behalf of said master devices; and  
       wherein at least one of said plurality of master devices couple to a second expansion bus. 
     
     
       2. A computer system as in claim  1 , wherein said expansion bus comprises a PCI bus, and said second expansion bus comprises an ISA bus. 
     
     
       3. A computer system as in claim  2 , wherein at least one of said master devices comprises an ISA controller residing in the bridge logic device. 
     
     
       4. A computer system as in claim  1 , wherein said second expansion bus comprises an IDE bus, and at least one of said master devices comprises an IDE controller integrated in the bridge logic device. 
     
     
       5. A computer system as in claim  1 , wherein said second expansion bus comprises a USB bus, and at least one of said master devices comprises a USB controller integrated in the bridge logic device. 
     
     
       6. A computer system as in claim  1 , wherein said plurality of master devices includes a re-map engine for completing cycles on said expansion bus addressed to legacy DMA channels. 
     
     
       7. A computer system, comprising: 
       a CPU;  
       a main memory;  
       at least one peripheral device coupled to said CPU and said memory by an expansion bus;  
       a bridge logic device connected to said expansion bus, said bridge logic being capable of running master cycles on said expansion bus;  
       wherein said bridge logic includes:  
       a plurality of master devices;  
       a common expansion bus master interface coupled to said expansion bus and to said plurality of master devices for executing expansion bus master cycles on behalf of said master devices; and  
       wherein said bridge logic includes an internal modular master expansion bus coupling said plurality of master devices to said common expansion bus master interface.  
     
     
       8. A computer system as in claim  7 , wherein said expansion bus comprises a PCI bus and said expansion bus master interface comprises a PCI master interface for translating internal modular master expansion bus cycles to master PCI cycles. 
     
     
       9. A computer system as in claim  8 , wherein said bridge logic device comprises a South bridge coupling the PCI bus to one or more secondary expansion busses. 
     
     
       10. A computer system as in claim  9 , further comprising a North bridge logic coupling said CPU and said main memory to the PCI bus. 
     
     
       11. A computer system as in claim  7 , wherein said bridge logic further includes: 
       an expansion bus target interface coupled to said expansion bus; and  
       an internal modular target expansion bus coupling said plurality of master devices to said expansion bus target interface.  
     
     
       12. A computer system, comprising: 
       a CPU;  
       a main memory;  
       a bridge logic device coupled to said CPU and said main memory by an expansion bus, said bridge logic coupling external peripheral devices to said expansion bus for running master cycles on said expansion bus to said main memory;  
       wherein said bridge logic includes:  
       a plurality of master devices;  
       a common internal modular master bus coupling said plurality of master devices to said expansion bus; and  
       an expansion bus master interface coupled to said expansion bus and to said common internal modular bus, said expansion bus master interface executing expansion bus master cycles on behalf of said master devices.  
     
     
       13. A computer system as in claim  12 , wherein said expansion bus comprises a PCI bus, and said expansion bus master interface comprises a PCI bus master interface executing PCI master cycles on behalf of said master devices. 
     
     
       14. A computer system as in claim  13 , wherein said bridge logic device comprises a South bridge coupling the PCI bus to one or more secondary expansion busses. 
     
     
       15. A computer system as in claim  14 , wherein said secondary expansion bus comprises an ISA bus, and one of said plurality of master devices comprises an ISA controller. 
     
     
       16. A computer system as in claim  14 , wherein said secondary expansion bus comprises a USB bus, and one of said plurality of master devices comprises a USB controller. 
     
     
       17. A computer system as in claim  14 , wherein said secondary expansion bus comprises an IDE bus, and one of said plurality of master devices comprises an IDE controller. 
     
     
       18. A computer system as in claim  12  wherein said b ridge logic further includes: 
       an expansion bus target interface coupled to said expansion bus; and  
       an internal modular target expansion bus coupling said plurality of master devices to said expansion bus target interface.  
     
     
       19. A computer system, comprising: 
       a CPU;  
       a main memory;  
       a North bridge logic device coupling a primary expansion bus to said CPU and said main memory;  
       a South bridge logic device connected to said expansion bus, said South bridge logic coupling at least one secondary expansion bus to said primary expansion bus for running master cycles originating from devices on said at least one secondary expansion bus on said primary expansion bus;  
       wherein said South bridge logic includes:  
       a control device for said at least one secondary expansion bus;  
       a common expansion bus master interface coupled to said primary expansion bus and to a corresponding control device for said at least one secondary expansion bus, said common expansion bus master interface executing expansion bus master cycles on behalf of said master devices; and  
       an internal modular master expansion bus coupled to said control device and to said common expansion bus master interface for transferring master cycles initiated by the control device to the expansion bus master interface.  
     
     
       20. A computer system as in claim  19 , wherein said primary expansion bus comprises a PCI bus, and said expansion bus master interface comprises a PCI master interface that translates master cycles on said internal modular master expansion bus to PCI master cycles. 
     
     
       21. A computer system as in claim  19 , wherein said at least one secondary expansion bus comprises one or more of the following busses: an ISA bus; a USB bus; or an IDE bus. 
     
     
       22. A computer system as in claim  19 , wherein said control device includes one or more of the following: a re-map engine; a floppy snoop logic; a USB controller; an ISA controller; or an IDE controller. 
     
     
       23. A computer system as in claim  19 , wherein said control device includes a re-map engine for completing cycles on said secondary expansion bus addressed to legacy DMA channels. 
     
     
       24. A computer system, comprising: 
       a CPU;  
       a main memory;  
       a bridge logic device coupled to said CPU and said main memory by an expansion bus, said bridge logic coupling external peripheral devices to said expansion bus for running master cycles on said expansion bus to said main memory;  
       wherein said bridge logic includes:  
       a plurality of master devices;  
       a common internal modular master bus coupling said plurality of master devices to said expansion bus;  
       a plurality of target devices; and  
       a common internal modular target bus coupling said plurality of target devices to said expansion bus.  
     
     
       25. A computer system as in claim  24 , wherein said expansion bus comprises a PCI bus, and said expansion bus master interface comprises a PCI master interface that translates master cycles on said internal modular master bus to PCI master cycles. 
     
     
       26. A computer system as in claim  24 , wherein said expansion bus comprises a PCI bus, and said expansion bus target interface comprises a PCI target interface that translates cycles on said PCI bus to internal modular target bus cycles. 
     
     
       27. A computer system as in claim  24 , wherein said plurality of master devices also comprise at least some of said plurality of target devices. 
     
     
       28. A computer system as in claim  27 , wherein said master devices include one or more of the following: a re-map engine; a floppy snoop logic; a USB controller; an ISA controller; or an IDE controller. 
     
     
       29. A method of running master cycles to a primary expansion bus from a master device within a bridge logic to a master interface within the bridge logic through an internal modular master expansion bus, comprising: 
       asserting a request for mastership from the master device to the master interface;  
       supplying transaction information to the master interface on the internal modular master expansion bus;  
       asserting a mastership grant signal from the master interface to the master device;  
       receiving the transaction information from the internal modular master expansion bus;  
       translating the transaction information to a protocol understood by the primary expansion bus;  
       transmitting the translated information to the primary expansion bus; and  
       transmitting a signal from the master interface to the master device indicating that the signals have been transferred to the primary expansion bus.  
     
     
       30. A method as in claim  29 , wherein said primary expansion bus comprises a PCI bus, and the translating step includes converting the transaction information to PCI signals. 
     
     
       31. A bridge logic device, comprising: 
       a plurality of master devices;  
       a common bus master interface capable of coupling to an external expansion bus and coupling to said plurality of master devices for executing bus master cycles on said external expansion bus on behalf of said master devices; and  
       an internal modular expansion bus coupling said plurality of master devices to said common bus master interface.  
     
     
       32. A bridge logic as in claim  31 , wherein at least one of said plurality of master devices is capable of coupling to a secondary expansion bus. 
     
     
       33. A bridge logic as in claim  34 , wherein said external expansion bus comprises a PCI bus, and said bus master interface translates internal modular expansion bus cycles to PCI cycles. 
     
     
       34. A bridge logic as in claim  33 , wherein said bridge logic comprises a South bridge coupling the PCI bus to the secondary expansion bus. 
     
     
       35. A bridge logic as in claim  32 , further comprising a target interface coupled to said external expansion bus. 
     
     
       36. A bridge logic as in claim  35 , further comprising: 
       an internal modular target expansion bus coupling said plurality of master devices to said target interface.