A/D converter having a dynamic encoder

Abstract

An A/D converter includes a resistor ladder for generating a plurality of reference potentials, a comparing section for comparing each of the reference potentials against an input analog signal to output a thermometric code, and a dynamic encoder composed of a combinational circuit to encode the thermometric code to a binary code by responding a clock signal. The A/D conversion is finished in a single clock cycle at a high speed, with a reduced number of elements and reduced power dissipation.

What is claimed is:  
     
       1. An analog-to-digital (A/D) converter comprising: 
       a reference voltage generator for generating a plurality of reference voltages;  
       a comparing section including a plurality of comparing elements each comparing an input analog signal against a corresponding one of said reference voltages to output a thermometric code; and  
       a dynamic encoder including a plurality of bit lines and a dynamic combinational circuit transferring said thermometric code to said bit lines by responding to a clock,  
       wherein said input analog signal is converted in a single clock cycle to a binary code generated on said bit lines and corresponding to a magnitude of said input analog signal;  
       wherein a rate of conversion is substantially independent of a number of bits to be output,  
       wherein each comparing element of said comparing section comprises a comparator and a level converter for amplifying an output from said comparator by responding to a clock signal, and,  
       wherein said level converter comprises CMOS transistors.  
     
     
       2. An A/D converter as defined in claim  1 , wherein said combinational circuit comprises a complementary signal generator activated by a clock signal. 
     
     
       3. An A/D converter as defined in claim  1 , wherein said level converter outputs a complementary signal. 
     
     
       4. An A/D converter as defined in claim  1 , wherein said dynamic encoder comprises a non-dichotomizing search encoder. 
     
     
       5. An A/D converter as defined in claim  1 , wherein said A/D converter contains an error correcting function. 
     
     
       6. An A/D converter as defined in claim  1 , wherein said A/D converter is devoid of latches. 
     
     
       7. An A/D converter as defined in claim  1 , wherein said thermometric code is converted to said binary code at a rate which is not dependent upon the number of bits to be output. 
     
     
       8. An A/D converter as defined in claim  1 , wherein the value of each bit of the output binary code does not depend on values of other bits. 
     
     
       9. An A/D converter as defined in claim  1 , wherein said dynamic encoder further comprises one of p-channel transistors and n-channel transistors. 
     
     
       10. An A/D converter as defined in claim  1 , wherein said reference voltage generator comprises a resistor ladder having a plurality of nodes adjacent two resistors and connected between a high voltage source and a low voltage source. 
     
     
       11. An A/D converter as defined in claim  1 , wherein said dynamic encoder further comprises an encoding section having n-channel transistors which connect said bit lines to a ground, a precharge section having p-channel transistors, and inverters at output ends of said bit lines. 
     
     
       12. An A/D converter as defined in claim  11 , wherein said dynamic encoder further comprises an array of complementary signal generators which have a dynamic configuration and receive outputs from said level converter. 
     
     
       13. An A/D converter as defined in claim  12 , wherein each said complementary signal generator comprises an inverter and two AND gates. 
     
     
       14. An analog-to-digital (A/D) converter comprising: 
       a reference voltage generator for generating a plurality of reference voltages;  
       a comparing section including a plurality of comparing elements each comparing an input analog signal against a corresponding one of said reference voltages to output a thermometric code; and  
       a dynamic encoder including a plurality of bit lines and a dynamic combinational circuit transferring said thermometric code to said bit lines by responding to a clock,  
       wherein said thermometric code is converted in a single clock cycle to a binary code generated on said bit lines and corresponding to a magnitude of said input analog signal, and  
       wherein said conversion is expressed by the Boolean algebra equation:          b   m     =       ∑     i   =   1       2     (     m   -   1     )              (       C        (     t   x     )       ×     t   y       )                       
       wherein N is a number of bits of said binary code, b m  is a m-th bit of said binary code counted from most significant bit (MSB), t x  is the x-th bit of said thermometric code counted from MSB, t y  is the y-th bit of said thermometric code counted from MSB, C(t x ) is a complement of t x , 0≦x≦ N −2, 1≦y≦2 N −1, x=2(i−1)×2 (N−m) ,y={2(i−1)+1}×2 (N−m) , and 1≦m≦N.  
     
     
       15. An A/D converter as defined in claim  14 , further comprising a digital adder for receiving a binary code of N bits from said dynamic encoder in synchronicity therewith to output a digital code having Y bits. 
     
     
       16. A method for converting a thermometric code to a binary code, comprising: 
       transferring a thermometric code to a plurality of bit lines by responding to a clock signal, wherein said conversion is expressed by the Boolean algebra equation:          b   m     =       ∑     i   =   1       2     (     m   -   1     )              (       C        (     t   x     )       ×     t   y       )                       
       wherein N is a number of bits of said binary code, b m , is a m-th bit of said binary code counted from most significant bit (MSB), t x  is the x-th bit of said thermometric code counted from MSB, t y  is the y-th bit of said thermometric code counted from MSB, C(t x ) is a complement of t x , 0≦x≦2 N −2, 1≦y≦2 N −1, x=2(i−1)×2 (N−m) , y={2(i−1)+1}×2 (N−m) , and 1≦m≦N.  
     
     
       17. A method as defined in claim  16 , wherein said conversion is conducted in a single clock cycle.