Low-noise voltage controlled oscillator

Abstract

A voltage controlled oscillator has first and second complementary output terminals. A first edge delay circuit has an input terminal, an output terminal, and a control input terminal. The input terminal is coupled to the first complementary output terminal. A first comparator has a first, second and third input terminal, an output terminal, and a control input terminal. The first input terminal is coupled to the output terminal of the first edge delay circuit. The second input terminal is coupled to the first complementary output terminal. The first comparator output terminal is coupled to the second complementary output terminal. A second edge delay circuit has an input terminal, an output terminal, and a control input terminal. The input terminal is coupled to the second complementary output terminal. A second comparator has a first, second and third input terminal, an output terminal, and a control input terminal. The first input terminal is coupled to the output terminal of the second edge delay circuit. The second input terminal is coupled to the second complementary output terminal. The second comparator output terminal is coupled to the first complementary output terminal. The control inputs of the first and second comparators and the first and second edge delay circuits are coupled together and adapted to allow each circuit to transition from at least one logic level to another logic level at a rate responsive to the magnitude of a signal applied thereto. A feedback circuit is coupled between the first and second complementary output terminals and the third inputs of the first and second comparator circuits.

What is claimed:  
     
       1. A voltage controlled oscillator having first and second complementary output terminals, comprising: 
       a first edge delay circuit having an input terminal, an output terminal, and a control input terminal, said input terminal being coupled to the first complementary output terminal, said first edge delay circuit being capable of delivering a signal on said output terminal that varies between first and second logic levels at first and second preselected rates in response to detecting a variation between first and second logic levels at said input terminal, said first edge delay circuit being capable of varying at least one of said first and second preselected rates in response to receiving a signal at said control input terminal;  
       a first comparator having a first input terminal, an output terminal, and a control input terminal, said first comparator first input terminal being coupled to the output terminal of the first edge delay circuit, said first comparator output terminal being coupled to the second complementary output terminal, said first comparator circuit being capable of delivering a signal on said output terminal that varies between first and second logic levels at first and second preselected rates in response to detecting a variation between first and second logic levels at said first input terminal, said first comparator being capable of varying at least one of said first and second preselected rates in response to receiving a signal at said control input terminal, said control input terminals of said first edge delay circuit and said first comparator being coupled together; and  
       a feedback circuit coupled between the second complementary output terminal and the first comparator circuit.  
     
     
       2. A voltage controlled oscillator, as set forth in claim  1 , wherein said first edge delay circuit includes a current source coupled between a first terminal of a voltage supply and the output terminal of the first edge delay circuit, said current source having a control input terminal coupled to the first edge delay circuit control input terminal. 
     
     
       3. A voltage controlled oscillator, as set forth in claim  2 , wherein said current source includes a transistor and a resistor serially coupled between the first terminal of the voltage supply and the output terminal of the first edge delay circuit, the transistor having a gate coupled to the control input terminal of the first edge delay circuit. 
     
     
       4. A voltage controlled oscillator, as set forth in claim  3 , wherein said transistor is an intrinsic transistor. 
     
     
       5. A voltage controlled oscillator, as set forth in claim  2 , including a transistor coupled between the output terminal of the first edge delay circuit and the voltage supply, said transistor having a gate coupled to the input terminal of the first edge delay circuit. 
     
     
       6. A voltage controlled oscillator, as set forth in claim  5 , including a capacitor coupled between the output terminal of the first edge delay circuit and the voltage supply. 
     
     
       7. A voltage controlled oscillator, as set forth in claim  1 , wherein said first comparator includes a second input terminal coupled to the first complementary output terminal, said first comparator being capable of pulling said second complementary output terminal to a first logic level in response to detecting a first logic level on said first complementary output terminal. 
     
     
       8. A voltage controlled oscillator, as set forth in claim  7 , wherein said comparator includes an AND gate and a NOR gate, the AND gate having a first input terminal coupled to the output terminal of the first edge delay circuit, a second input terminal coupled to the feedback circuit, and an output terminal, the NOR gate having a first input terminal coupled to the output terminal of the AND gate and a second input terminal coupled to the first complementary output terminal. 
     
     
       9. A voltage controlled oscillator, as set forth in claim  1 , wherein said first comparator includes a current source coupled between a first terminal of a voltage supply and the output terminal of the first comparator, said current source having a control input terminal coupled to the first comparator control input terminal. 
     
     
       10. A voltage controlled oscillator, as set forth in claim  9 , wherein said current source includes a transistor and a resistor serially coupled between the first terminal of the voltage supply and the output terminal of the first comparator, the transistor having a gate coupled to the control input terminal of the first comparator. 
     
     
       11. A voltage controlled oscillator, as set forth in claim  10 , wherein said transistor is an intrinsic transistor. 
     
     
       12. A voltage controlled oscillator, as set forth in claim  10 , including a transistor coupled between the output terminal of the first comparator and the voltage supply, said transistor having a gate coupled to the input terminal of the first comparator. 
     
     
       13. A voltage controlled oscillator, as set forth in claim  5 , including at least one diode and a second terminal of the voltage supply. 
     
     
       14. A voltage controlled oscillator having first and second complementary output terminals, comprising: 
       a first edge delay circuit having an input terminal, an output terminal, and a control input terminal, said input terminal being coupled to the first complementary output terminal;  
       a first comparator having a first, second and third input terminals, an output terminal, and a control input terminal, said first input terminal being coupled to the output terminal of the first edge delay circuit, said second input terminal being coupled to the first complementary output terminal, and said first comparator output terminal being coupled to the second complementary output terminal;  
       a second edge delay circuit; having an input terminal, an output terminal, and a control input terminal, said input terminal being coupled to the second complementary output terminal;  
       a second comparator having a first, second and third input terminals, an output terminal, and a control input terminal, said first input terminal being coupled to the output terminal of the second edge delay circuit, said second input terminal being coupled to the second complementary output terminal, and said second comparator output terminal being coupled to the first complementary output terminal, the control inputs of said first and second comparators and said first and second edge delay circuits being coupled together and adapted to allow each circuit to transition from at least one logic level to another logic level at a rate responsive to the magnitude of a signal applied thereto; and  
       a feedback circuit coupled between the first and second complementary output terminals and the third inputs of the first and second comparator circuit.  
     
     
       15. A voltage controlled oscillator, as set forth in claim  14 , wherein said first edge delay circuit includes a current source coupled between a first terminal of a voltage supply and the output terminal of the first edge delay circuit, said current source having a control input terminal coupled to the first edge delay circuit control input terminal. 
     
     
       16. A voltage controlled oscillator, as set forth in claim  15 , wherein said current source includes a transistor and a resistor serially coupled between the first terminal of the voltage supply and the output terminal of the first edge delay circuit, the transistor having a gate coupled to the control input terminal of the first edge delay circuit. 
     
     
       17. A voltage controlled oscillator, as set forth in claim  16 , wherein said transistor is an intrinsic transistor. 
     
     
       18. A voltage controlled oscillator, as set forth in claim  15 , including a transistor coupled between the output terminal of the first edge delay circuit and the voltage supply, said transistor having a gate coupled to the input terminal of the first edge delay circuit.