Signature compression circuit and method

Abstract

A parallel signature compression circuit allows the error effect of at least one of two repetitive error patterns to be transferred to a cell other than the cell where the error effect is counterbalanced. In an embodiment, a signature pattern from a circuit to be tested is latched, and then the latched pattern is compressed two or more times until a next signature pattern is outputted from the circuit to be test. The compression is performed by shifting the latched pattern serially by use of a multiple input signature register.

What is claimed is:  
     
       1. A compression circuit for generating signature patterns from response data patterns that are produced at a first frequency, said compression circuit comprising: 
       a clock generator circuit that generates a clock signal having a second frequency at least twice as great as the first frequency; and  
       a digital data compressor circuit that compresses the response data patterns in synchronism with the clock signal such that a respective one of the response data patterns is compressed at least two times to produce a respective signature pattern.  
     
     
       2. The compression circuit of claim  1 , wherein said digital data compressor circuit comprises a multiple input signature register which compresses the response data patterns in synchronism with the clock signal. 
     
     
       3. The compression circuit of claim  2 , wherein said multiple input signature register includes at least one feedback tap. 
     
     
       4. The compression circuit of claim  1 , wherein the response data patterns are produced by an electronic circuit, and wherein said digital data compressor is integrated in a single integrated circuit chip with said electronic circuit. 
     
     
       5. The compression circuit of claim  4 , wherein said clock generator is included in said single integrated circuit chip. 
     
     
       6. The compression circuit of claim  1 , further comprising a buffer circuit which latches response data at the first frequency to generate the response data patterns at the first frequency. 
     
     
       7. The compression circuit of claim  6 , wherein the response data is produced by an electronic circuit, and wherein said buffer circuit, said clock generator circuit and said digital data compressor circuit are included in a single integrated circuit chip with said electronic circuit. 
     
     
       8. The compression circuit of claim  7 , wherein said integrated circuit chip is a memory chip. 
     
     
       9. A method for generating signature patterns from response data produced by a circuit to be tested, the method comprising the steps of: 
       latching the response data to produce a first response data pattern;  
       compressing the first response data pattern two or more times to produce a first signature pattern from the first response data pattern;  
       latching the response data to produce a second response data pattern; and  
       compressing the second response data pattern to produce a second signature pattern.  
     
     
       10. The method of claim  9 : 
       wherein said step of latching the response data to produce a first response data pattern comprises the step of applying the first response data pattern to a multiple input shift register (MISR);  
       wherein said step of compressing the first response data pattern comprises the step of clocking the MISR at least two times while the first response data pattern is applied to the MISR to generate the first signature pattern; and  
       wherein said step of latching the response data to produce a second response data pattern comprises the step of applying the second response data pattern to the MISR.  
     
     
       11. A method according to claim  10 , wherein the step of applying the first response data pattern to a multiple input shift register (MISR) comprises the step of applying the first response data pattern to the MISR until the second response data pattern is applied to the MISR. 
     
     
       12. A compression circuit for compressing response data from an electronic circuit to be tested, said compression circuit comprising: 
       a signal generator circuit that generates a first signal having a first frequency;  
       a latch circuit, responsive to the first signal, that latches the response data to produce response data patterns at the first frequency;  
       a frequency multiplier circuit, responsive to the first signal, that generates a second signal having a second frequency which is an integer multiple of the first frequency; and  
       a compressor circuit, responsive to the second signal, that compresses each of the response data patterns at least two times in synchronism with the second signal to generate a respective signature pattern for a respective response data pattern.  
     
     
       13. The compression circuit of claim  12 , wherein said compressor circuit comprises a multiple input signature register which compresses the response data patterns in synchronism with the second signal. 
     
     
       14. The compression circuit of claim  13 , wherein said multiple input signature register includes at least one feedback tap. 
     
     
       15. The compression circuit of claim  12 , wherein said frequency multiplier circuit comprises one of a frequency doubler, a frequency tripler, and frequency quadrupler. 
     
     
       16. A method of generating signature patterns from response data, the method comprising the steps of: 
       latching the response data to produce response data patterns at a first frequency; and  
       compressing the response data patterns at a second frequency at least two times greater than the first frequency to produce respective signature patterns for respective ones of the response data patterns.  
     
     
       17. The method of claim  16 : 
       wherein the step of latching comprises the step of applying the response data patterns to a multiple input shift register (MISR) at the first frequency; and  
       wherein the step of compressing comprises clocking the MISR at the second frequency.