Real-time reconfigurable vision computing system

Abstract

An image processing system uses an FPGA and an external memory to form neighborhoods for image processing. The FPGA is connected to the external memory in a way that reuses address lines, and increases the effective bandwidth of the operation.

What is claimed is:  
     
       1. A computer system, comprising: 
       a field-programmable gate array; and  
       an external memory, external to said field-programmable gate array;  
       said field-programmable gate array including configurable logic blocks which are configured in a way to share address lines that interface with said external memory; and  
       wherein said configurable logic blocks are programmed to define a memory location, define a fixed increment for said memory location, and read data using said increment.  
     
     
       2. A system as in claim  1 , wherein said configurable logic blocks are programmed to define a memory location, define at fixed increment for said memory location and read data using said increment to provide temporary storage for information needed to process a window of information.