US6261893B1ExpiredUtility

Method for forming a magnetic layer of magnetic random access memory

78
Assignee: MOSEL VITELIC INCPriority: Aug 30, 2000Filed: Oct 12, 2000Granted: Jul 17, 2001
Est. expiryAug 30, 2020(expired)· nominal 20-yr term from priority
B82Y 10/00H10B 61/00
78
PatentIndex Score
40
Cited by
2
References
12
Claims

Abstract

The present invention relates to a method for forming a magnetic layer of magnetic random access memory. In short, the method comprises following steps: providing a substrate; forming metal structures on substrate; forming a stop layer on substrate and mostly conformally covers metal structures; forming a buffer layer which mostly conformally covers stop layer; forming a dielectric layer on buffer layer where thickness of dielectric layer is larger than height of metal structures; planarizing the surface of said dielectric layer; and forming a magnetic layer on dielectric layer. Moreover, some essential key-points of the method are dielectric layer is more sensitive to said stop layer than buffer layer and gap fill ability of dielectric layer is better than gap fill ability of buffer layer.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A method for forming a magnetic layer of magnetic random access memory, said method comprising following steps: 
       providing a substrate which comprises a transistor inside;  
       forming a plurality of metal structures on said substrate;  
       forming a stop layer on said substrate, wherein said stop layer mostly conformally covers said metal structures;  
       forming a buffer layer which mostly conformally covers said stop layer;  
       forming a dielectric layer on said buffer layer, wherein thickness of said dielectric layer is larger than height of said metal structures;  
       performing a removal process to remove both part of said dielectric layer and part of said buffer layer to let the top surface of said metal structures is only covered by said stop layer; and  
       forming a magnetic layer on said dielectric layer.  
     
     
       2. The method according to claim  1 , wherein said substrate further comprising a circuitry which is fabricated by a complimentary metal oxide semiconductor process. 
     
     
       3. The method according to claim  1 , wherein said metal structures are metal lines. 
     
     
       4. The method according to claim  1 , wherein said stop layer is silicon nitride layer. 
     
     
       5. The method according to claim  1 , wherein said buffer layer is a low O3 tetraethyl-orthosilicate SiO2 layer. 
     
     
       6. The method according to claim  1 , wherein said buffer layer is a plasma enhanced silicon nitride layer. 
     
     
       7. The method according to claim  1 , wherein thickness of said buffer layer is about between 800 angstroms to 2000 angstroms. 
     
     
       8. The method according to claim  1 , wherein thickness of said dielectric layer is larger than about 4000 angstroms. 
     
     
       9. The method according to claim  1 , wherein said dielectric layer is a high O3 tetraethyl-orthosilicate SiO2 layer. 
     
     
       10. The method according to claim  1 , wherein thickness of said stop layer on the top surface of said metal structure is about 1500 angstroms to 2000 angstroms after said removal process is finished. 
     
     
       11. The method according to claim  1 , wherein said removal process is an etching process. 
     
     
       12. The method according to claim  1 , wherein said removal process is a chemical mechanical polish process.

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