Method of manufacturing a trench isolation region in a semiconductor device

Abstract

A method of manufacturing a semiconductor device in which a groove is not formed at edges of a trench isolation region is provided. The semiconductor device includes an active region and a trench isolation region formed on a semiconductor substrate. The trench isolation region is comprised of a side wall insulation layer which is a thermal oxide, an exposure prevention layer which is a high temperature oxide, and an insulator burial layer which is a low temperature oxide. The densified exposure prevention layer is formed between the side wall insulation layer and the insulator burial layer, thereby preventing a groove exposing the surface of the semiconductor substrate from being formed between the active region where a gate electrode is formed and the trench isolation region. Therefore, when a voltage less than a threshold voltage is applied to the gate electrode, a channel is not formed under the gate electrode, thereby preventing current flow.

What is claimed is:  
     
       1. A method for manufacturing a semiconductor device comprising: 
       forming a trench by etching a portion of a semiconductor substrate;  
       recovering the surface of the semiconductor substrate damaged due to etching by forming a side wall insulation layer at side walls and on a bottom portion of the trench;  
       forming an exposure prevention layer of oxide on the side wall insulation layer to prevent the side walls of the trench from being exposed to a subsequent etching; and  
       forming an insulator burial layer by depositing an insulator into the trench where the side wall insulation layer and the exposure prevention layer are formed, the insulator burial layer being formed less dense than the exposure prevention layer.  
     
     
       2. The method according to claim  1 , wherein the side wall insulation layer is formed by thermal oxidation. 
     
     
       3. The method according to claim  1 , wherein the side wall insulation layer is formed to a thickness of 200-500 Å. 
     
     
       4. The method according to claim  1 , wherein the exposure prevention layer is formed by a chemical vapor deposition process. 
     
     
       5. The method according to claim  4 , wherein the chemical vapor deposition process is performed at a temperature of 800° C. or above. 
     
     
       6. The method according to claim  1 , wherein the forming the exposure prevention layer comprises: 
       depositing polysilicon over the entire surface of the semiconductor substrate where the side wall insulation layer is formed; and  
       thermally oxidizing the deposited polysilicon.  
     
     
       7. The method according to claim  1 , wherein the exposure prevention layer is formed to a thickness of 500-2000 Å. 
     
     
       8. The method according to claim  1 , wherein the insulator burial layer is formed by a chemical vapor deposition process. 
     
     
       9. The method according to claim  8 , wherein the insulator burial layer is formed at a low temperature of 400° C. or below. 
     
     
       10. The method according to claim  8 , wherein after forming the insulator burial layer, the semiconductor substrate is annealed at a temperature of 900-1100° C. 
     
     
       11. The method according to claim  1 , wherein the forming the trench comprises: 
       sequentially depositing a buffer layer and a mask insulation layer on the semiconductor substrate;  
       patterning the mask insulation layer and the buffer layer; and  
       forming the trench by etching the semiconductor substrate using the patterned buffer layer and mask insulation layer as a mask, and  
       wherein the forming the insulator burial layer is followed by planarizing the insulator burial layer by a CMP process and removing the mask insulation layer and the buffer layer.  
     
     
       12. The method according to claim  11 , wherein the exposure prevention layer is at least twice as thick as the buffer layer, and at least as thick as the side wall insulation layer. 
     
     
       13. The method according to claim  11 , wherein upper portions of the exposure prevention layer and the insulator burial layer are simultaneously etched while the buffer layer is removed. 
     
     
       14. The method according to claim  13 , wherein in removing the buffer layer, the exposure prevention layer and the insulator burial layer, the insulator burial layer is etched more than the buffer layer and the exposure prevention layer is etched less than the insulator burial layer.