Efficient fabrication process for dual well type structures

Abstract

An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low voltage and high voltage p-channel transistors to be formed in a single substrate. One mask is used for forming a diffusion well, a second mask for both forming a retrograde well and doping the well to achieve an intermediate threshold voltage in that well, and a third mask for both differentiating the gate oxides for the low voltage devices and doping the threshold voltages to achieve the final threshold voltages.

What is claimed as new and desired to be protected by Letters Patent of the United States is:  
     
       1. A method for forming an integrated circuit with at least two types of wells, the method comprising the steps of: 
       providing a first mask with a first opening over a substrate;  
       forming a first well of a first well type in the substrate through the first opening;  
       forming a first oxide layer over the substrate;  
       providing a second mask with a second opening over the substrate;  
       forming a second well of a second well type in the substrate through the second opening;  
       doping the second well through the second opening to adjust a voltage threshold of a device to be formed in the second well to a first value;  
       providing a third mask with third and fourth openings;  
       modifying the thickness of the first oxide layer in areas corresponding to the third and fourth openings;  
       doping areas corresponding to the third and fourth openings to adjust voltage thresholds of devices to be formed in areas corresponding to the third and fourth openings; and  
       forming a first device in the first well, a second device in the second well, and a third device in an area of the substrate corresponding to the fourth opening.  
     
     
       2. The method of claim  1 , wherein the first well is a diffusion well formed by an ion implantation process at an energy of less than approximately 200 keV. 
     
     
       3. The method of claim  1 , wherein the second well is a retrograde well formed by an ion implantation process at an energy of greater than approximately 240 keV. 
     
     
       4. The method of claim  1 , wherein the first device is formed by forming a gate stack, a source area on one side of the gate stack and a drain area on another side of the gate stack. 
     
     
       5. The method of claim  1 , wherein the second device is formed by forming a gate stack, a source area on one side of the gate stack and a drain area on another side of the gate stack. 
     
     
       6. The method of claim  1 , wherein the third device is formed by forming a gate stack, a source area on one side of the gate stack and a drain area on another side of the gate stack. 
     
     
       7. The method of claim  1 , wherein the first well is formed by implanting n-type ions. 
     
     
       8. The method of claim  1 , wherein the first well is formed by implanting p-type ions. 
     
     
       9. The method of claim  1 , wherein the second well is formed by implanting n-type ions. 
     
     
       10. The method of claim  1 , wherein the second well is formed by implanting p-type ions. 
     
     
       11. A method for forming a first device of a first conductivity type and of a first voltage threshold, a second device of the first conductivity type and a second voltage threshold, and a third device of a second conductivity type and first voltage threshold, the method comprising the steps of: 
       providing a first mask with a first opening corresponding the location of the first device on a substrate of the first conductivity type;  
       forming a first well of a first well type and the second conductivity type through the first opening;  
       forming a first oxide layer over the substrate;  
       providing a second mask with a second opening corresponding to the location of the second device on the substrate;  
       forming a second well of a second well type and the second conductivity type through the second opening;  
       doping the second well through the second opening to adjust a voltage threshold of the second device to an intermediate value;  
       providing a third mask with a third opening corresponding to the location of the second device and a fourth opening corresponding to the location of the third device on the substrate;  
       adjusting the thickness of oxide layers on the substrate in the third and fourth openings;  
       doping areas exposed by the third and fourth openings to adjust voltage thresholds of the second and third devices, respectively;  
       growing an additional oxide layer on the substrate; and  
       forming the first, second and third devices in the first well, the second well, and in the area corresponding to the fourth opening, respectively.  
     
     
       12. The method of claim  11 , wherein the devices are formed by forming a gate stack, a source area on one side of the gate stack and a drain area on another side of the gate stack. 
     
     
       13. The method of claim  11 , wherein the first voltage is higher than the second voltage. 
     
     
       14. The method of claim  11 , wherein the wells are formed by implanting n-type material. 
     
     
       15. The method of claim  11 , wherein the first type of well is a diffusion well formed by ion implantation at an energy lower than approximately 200 keV. 
     
     
       16. The method of claim  11 , wherein the second type of well is a retrograde well formed by ion implantation at an energy higher than approximately 240 keV. 
     
     
       17. A method for forming an integrated circuit on a substrate, the method comprising the steps of. 
       providing a first mask on the substrate with a first opening;  
       forming an n-type diffusion well through the first opening;  
       removing the first mask;  
       forming isolation areas in the substrate;  
       growing a first gate oxide layer over the substrate;  
       providing a second mask on the substrate with a second opening;  
       forming a n-type retrograde well through the second opening;  
       doping the retrograde well through the second opening to adjust the voltage threshold of a p-channel transistor to be formed in the well at a later time to an intermediate value;  
       removing the second mask;  
       providing a third mask on the substrate with a third opening over the retrograde well and a fourth opening over an area of the substrate on which an n-channel transistor is to be formed;  
       reducing the thickness of the first gate oxide layer in the areas corresponding to the third and fourth openings;  
       doping the retrograde well through the second opening and the area of the substrate on which the p-channel transistor is to be formed through the fourth opening such that the voltage threshold of the n-channel transistor and p-channel transistor are at desired values;  
       removing the third mask;  
       forming a second gate oxide layer on the substrate such that the total thickness of the gate oxide layers in areas not corresponding to the third and fourth openings corresponds to transistors with a first voltage threshold and the thickness of the gate oxide layers in areas corresponding to the third and fourth openings corresponds to transistors of a second voltage threshold; and  
       forming transistors on the substrate in the first well, the second well, and in an area corresponding to the fourth opening.  
     
     
       18. The method of claim  17 , wherein the first voltage is higher than the second voltage. 
     
     
       19. The method of claim  17 , wherein the isolation areas are formed by a shallow trench isolation process. 
     
     
       20. The method of claim  17 , wherein the reducing step is performed by removing all gate oxide in areas corresponding to the third and fourth openings. 
     
     
       21. The method of claim  17 , wherein the gate oxide layers are formed using a thermal process. 
     
     
       22. The method of claim  17 , wherein the integrated circuit is a memory circuit. 
     
     
       23. The method of claim  22 , wherein the memory circuit is a static random access memory circuit. 
     
     
       24. The method of claim  23 , wherein the static random access memory circuit comprises memory cells comprising two p-channel transistors formed in an n-well and four n-channel transistors. 
     
     
       25. The method of claim  24 , wherein the memory cells comprise low voltage transistors and peripheral memory circuitry comprises high voltage transistors. 
     
     
       26. A method for forming an integrated circuit with at least two types of wells, the method comprising the steps of: 
       providing a first mask with a first opening over a substrate;  
       forming a first well of a first well type in the substrate through the first opening;  
       forming a first oxide layer over the substrate;  
       providing a second mask with a second opening over the first oxide layer;  
       forming a second well of a second well type in the substrate through the second opening by an ion implantation process at an energy of less than approximately 200 keV followed by thermal diffusion;  
       subsequently doping the second well through the second opening to adjust a voltage threshold of a device to be formed in the second well to a first value;  
       providing a third mask with third and fourth openings;  
       modifying the thickness of the first oxide layer areas corresponding to the third and fourth openings;  
       doping areas corresponding to the third and fourth openings to adjust voltage thresholds of devices to be formed in areas corresponding to the third and fourth openings; and forming a first device in the first well, a second device in the second well, a third device in an area of the substrate corresponding to the third opening, and a fourth device in an area of the substrate corresponding to the fourth opening.