Method for making a semiconductor device

Abstract

A method for making a semiconductor device includes forming a plurality of transistors in a semiconductor substrate, forming a first dielectric layer overlying the semiconductor substrate, and selectively etching the first dielectric layer to form a first opening exposing a first transistor portion and a second transistor portion. Conducting material is deposited into the first opening to define a merged contact between the first transistor portion and the second transistor portion. The method further includes forming a second dielectric layer overlying the first dielectric layer and the merged contact, and selectively etching the second dielectric layer to form a second opening exposing the merged contact, and while selectively etching the second and first dielectric layers to form a third opening exposing a source/drain region of a third transistor to define a self-aligned contact. Conducting material is deposited into the second opening to define a first via with the merged contact, and conducting material is also deposited into the third opening to define a second via with the source/drain region of the third transistor. The self-aligned contact and the merged contact are formed using a reduced number of masks and masking steps.

That which is claimed is:  
     
       1. A method for making a semiconductor device comprising the steps of: 
       forming a plurality of transistors in a semiconductor substrate;  
       forming a first dielectric layer overlying the semiconductor substrate;  
       selectively etching the first dielectric layer to form a first opening exposing a first transistor portion and a second transistor portion;  
       depositing conducting material into the first opening to define a merged contact between the first transistor portion and the second transistor portion;  
       forming a second dielectric layer overlying the first dielectric layer and the merged contact;  
       selectively etching the second dielectric layer to form a second opening exposing the merged contact, and while selectively etching the second and first dielectric layers to form a third opening exposing a source/drain region of a third transistor; and  
       depositing conducting material into the second opening to define a first via with the merged contact, and while depositing conducting material into the third opening to define a second via with the source/drain region of the third transistor to define a self-aligned contact.  
     
     
       2. A method according to claim  1  wherein selectively etching the first dielectric layer further comprises forming a fourth opening exposing a fourth transistor portion; and further comprising forming a first connection with the fourth transistor portion by depositing conducting material into the fourth opening. 
     
     
       3. A method according to claim  2  wherein forming a second dielectric layer also overlies the first connection; wherein selectively etching the second dielectric layer further comprises defining a fifth opening exposing a portion of the first connection; and wherein depositing conducting material further comprises forming a third via with the first connection. 
     
     
       4. A method according to claim  1  wherein the first dielectric layer has a thickness substantially equal to a thickness of the second dielectric layer. 
     
     
       5. A method according to claim  1  wherein the first dielectric layer has a thickness less than about 500 nm. 
     
     
       6. A method according to claim  1  further comprising the step of planarizing an upper surface of the first dielectric layer and the merged contact. 
     
     
       7. A method according to claim  6  wherein the step of planarizing comprises chemical mechanical polishing. 
     
     
       8. A method according to claim  1  wherein the conducting material comprises tungsten. 
     
     
       9. A method according to claim  1  wherein the first and second transistor portions comprise at least one of a source/drain region and a gate. 
     
     
       10. A method according to claim  1  wherein the plurality of transistors are connected together define at least one memory cell in an SRAM. 
     
     
       11. A method according to claim  1  wherein the first and second dielectric layers comprise silicon dioxide. 
     
     
       12. A method for making a semiconductor device comprising the steps of: 
       forming a plurality of transistors in a semiconductor substrate;  
       forming a first dielectric layer overlying the semiconductor substrate;  
       selectively etching the first dielectric layer to form a first opening exposing a first transistor portion and a second transistor portion;  
       depositing conducting material into the first opening to define a merged contact between the first transistor portion and the second transistor portion;  
       forming a second dielectric layer overlying the first dielectric layer and the merged contact;  
       selectively etching the second dielectric layer to form a second opening exposing the merged contact; and  
       depositing conducting material into the second opening to define a first via with the merged contact.  
     
     
       13. A method according to claim  12  wherein selectively etching the second dielectric layer further comprises selectively etching the second and first dielectric layers to form a third opening exposing a source/drain region of a third transistor; and wherein depositing conducting material into the second opening further comprises depositing conducting material into the third opening to define a second via with the source/drain region of the third transistor to define a self-aligned contact. 
     
     
       14. A method according to claim  12  wherein selectively etching the first dielectric layer further comprises forming a fourth opening exposing a fourth transistor portion; and further comprising forming a first connect ion with the fourth transistor portion by depositing conducting material into the fourth opening. 
     
     
       15. A method according to claim  14  wherein forming a second dielectric layer also overlies the first connection; wherein selectively etching the second dielectric layer further comprises defining a fifth opening exposing a portion of the first connection; and wherein depositing conducting material further comprises forming a third via with the first connection. 
     
     
       16. A method according to claim  12  wherein the first dielectric layer has a thickness substantially equal to a thickness of the second dielectric layer. 
     
     
       17. A method according to claim  12  wherein the first dielectric layer has a thickness less than about 500 nm. 
     
     
       18. A method according to claim  12  further comprising the step of planarizing an upper surface of the first dielectric layer and the merged contact. 
     
     
       19. A method according to claim  12  further comprising the step of planarizing an upper surface of the second dielectric layer and the first and second vias. 
     
     
       20. A method according to claim  12  wherein the conducting material comprises tungsten. 
     
     
       21. A method according to claim  12  wherein the first and second transistor portions comprise at least one of a source/drain region and a gate. 
     
     
       22. A method according to claim  12  wherein the plurality of transistors are connected together define at least one memory cell in an SRAM. 
     
     
       23. A method according to claim  12  wherein the first and second dielectric layers comprise silicon dioxide. 
     
     
       24. A method for making a memory comprising the steps of: 
       forming a plurality of memory cells in a semiconductor substrate, each memory cell comprising at least one transistor;  
       forming a first dielectric layer overlying the semiconductor substrate;  
       selectively etching the first dielectric layer to form a first opening exposing a first transistor portion and a second transistor portion;  
       depositing conducting material into the first opening to define a merged contact between the first transistor portion and the second transistor portion;  
       forming a second dielectric layer overlying the first dielectric layer and the merged contact;  
       selectively etching the second dielectric layer to form a second opening exposing the merged contact, and while selectively etching the second and first dielectric layers to form a third opening exposing a source/drain region of a third transistor; and  
       depositing conducting material into the second opening to define a first via with the merged contact, and while depositing conducting material into the third opening to define a second via with the source/drain region of the third transistor to define a self-aligned contact.  
     
     
       25. A method according to claim  24  wherein selectively etching the first dielectric layer further comprises forming a fourth opening exposing a fourth transistor portion; and further comprising forming a first connect ion with the fourth transistor portion by depositing conducting material into the fourth opening. 
     
     
       26. A method according to claim  25  wherein forming a second dielectric layer also overlies the first connection; wherein selectively etching the second dielectric layer further comprises defining a fifth opening exposing a portion of the first connection; and wherein depositing conducting material further comprises forming a third via with the first connection. 
     
     
       27. A method according to claim  24  wherein the first dielectric layer has a thickness substantially equal to a thickness of the second dielectric layer. 
     
     
       28. A method according to claim  24  wherein the first dielectric layer has a thickness less than about 500 nm. 
     
     
       29. A method according to claim  24  further comprising the step of planarizing an upper surface of the first dielectric layer and the merged contact. 
     
     
       30. A method according to claim  24  further comprising the step of planarizing an upper surface of the second dielectric layer and the first and second vias. 
     
     
       31. A method according to claim  24  wherein the conducting material comprises tungsten. 
     
     
       32. A method according to claim  24  wherein the plurality of transistors are connected together define at least one memory cell in an SRAM. 
     
     
       33. A method according to claim  24  wherein the first and second dielectric layers comprise silicon dioxide.