Integrated circuit device having a planar interlevel dielectric layer

Abstract

An integrated circuit includes a conductive layer adjacent a semiconductor substrate. The conductive layer includes conductive lines having gaps therebetween. A fluoro-silicate glass (FSG) layer is over the patterned conductive layer fills the gaps between conductive lines. Also, an undoped oxide layer is on the FSG layer. Peaks of the FSG layer which overlie the conductive metal lines have been reduced by CMP. Thus, a subsequent conductive layer is substantially protected from exposure to fluorine from the FSG layer.

That which is claimed is:  
     
       1. An integrated circuit device comprising: 
       a semiconductor substrate;  
       a conductive layer adjacent the semiconductor substrate, the conductive layer including patterned conductive lines having gaps therebetween, and at least some of the patterned conductive lines having different widths; and  
       a composite dielectric layer comprising  
       a fluoro-silicate glass (FSG) layer over the patterned conductive lines and filling the gaps between the patterned conductive lines, the FSG layer having peaks which overlie the conductive lines and which have a substantially uniform height above the conductive layer, and  
       a planar undoped oxide layer on the FSG layer.  
     
     
       2. The device according to claim  1 , further comprising a protective dielectric layer on the patterned conductive lines. 
     
     
       3. The device according to claim  1 , wherein the undoped oxide layer comprises an undoped-silicate glass layer (USG). 
     
     
       4. The device according to claim  1 , wherein the conductive layer is a metal layer and comprises at least one of aluminum and copper. 
     
     
       5. The device according to claim  1 , wherein the FSG layer has a thickness of at least 100 nanometers higher than the thickness of the conductive layer. 
     
     
       6. An integrated circuit device comprising: 
       a semiconductor substrate;  
       a first metal layer adjacent the semiconductor substrate, the first metal layer including a plurality of patterned metal lines having gaps therebetween, and at least some of the plurality of patterned metal lines having different widths;  
       a composite dielectric layer comprising  
       a fluoro-silicate glass (FSG) layer over the plurality of patterned metal lines and filling the gaps between the plurality of patterned metal lines, and  
       a planar undoped oxide layer on the FSG layer; and  
       a second metal layer adjacent the planar undoped oxide layer;  
       the FSG layer having a plurality of peaks each of which is above one of the plurality of patterned metal lines and each of which has substantially a same height above the first metal layer to protect the second metal layer from exposure to fluorine from the FSG layer.  
     
     
       7. The device according to claim  6 , further comprising a protective dielectric layer on the patterned metal lines. 
     
     
       8. The device according to claim  6 , wherein the undoped oxide layer comprises an undoped-silicate glass layer (USG). 
     
     
       9. The dielectric according to claim  6 , wherein the first metal layer comprises at least one of aluminum and copper. 
     
     
       10. The device according to claim  6 , wherein the FSG layer has a thickness of at least 100 nanometers higher than the thickness of the first metal layer. 
     
     
       11. A composite planar interlevel dielectric for an integrated circuit including a plurality of patterned metal lines having gaps therebetween, and at least some of the plurality of patterned metal lines having different widths, the dielectric comprising: 
       a fluoro-silicate glass (FSG) layer over the plurality of patterned metal lines and filling the gaps between the plurality of patterned metal lines, the FSG layer having a plurality of peaks each of which is above one of the plurality of patterned metal lines and each of which has substantially a same height above the plurality of patterned metal lines to protect a subsequent metal layer from exposure to fluorine from the FGS layer; and  
       a planar undoped oxide layer on the FSG layer.  
     
     
       12. The dielectric according to claim  11 , further comprising a protective oxide layer on the plurality of patterned metal lines. 
     
     
       13. The dielectric according to claim  11 , wherein the undoped oxide layer comprises an undoped-silicate glass layer (USG). 
     
     
       14. The dielectric according to claim  11 , wherein the FSG layer has a thickness of at least 100 nanometers higher than the thickness of the plurality of patterned metal lines.