US6275835B1ExpiredUtility

Finite impulse response filter and method

60
Assignee: MOTOROLA INCPriority: Feb 16, 1999Filed: Feb 16, 1999Granted: Aug 14, 2001
Est. expiryFeb 16, 2019(expired)· nominal 20-yr term from priority
H03H 17/06
60
PatentIndex Score
17
Cited by
1
References
6
Claims

Abstract

A finite impulse response filter ( 90 ) has a data memory bank ( 92, 350 ) for storing data vectors and a coefficient memory bank ( 91, 300 ) for storing coefficient vectors. Filtering is done by multiplying data words by coefficient words, and summing the results. The finite impulse response filter ( 90 ) operates in different modes, according to the type of data vector and coefficient vector. In two modes of operation consecutive elements of the data vector ( 360-369, 460-475 ) are stored in consecutive odd memory words ( 380, 382..396 ) within the data memory bank ( 92, 350 ). In other modes consecutive elements of the data vector are stored in consecutive memory words ( 380-397 ) in the data memory bank ( 92, 350 ). Consecutive coefficient vector elements ( 310-319, 410-419 ) are stored in the consecutive memory words ( 340-349 ) in coefficient memory bank ( 91, 300 ), wherein coefficient elements can be stored in reverse or forward order. The data memory bank ( 92, 350 ) is coupled to a data address generator ( 200 ) comprising of counter ( 209 ), two multiplexers ( 220, 222 ), a XOR gate ( 270 ) and an AND gate ( 290 ).

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A finite response impulse filter comprising: 
       data memory bank, for storing a data vector;  
       a coefficient memory bank, for storing a coefficients vector;  
       a data address generator, coupled to the data memory bank, for generating memory addresses, resulting in reading or writing data stored within data memory bank;  
       wherein the finite response impulse filter is coupled to a control unit; wherein the control unit controls reading and writing from the data memory bank and the coefficient memory bank, in a plurality of modes;  
       wherein in a first mode of operation, the data vector and the coefficient vector are pure real;  
       wherein in a second mode of operation, the coefficient vector has alternating real and imaginary elements, and the data vector has complex elements;  
       wherein all the other possible combinations of data vector and coefficient vector are dealt in a third mode;  
       wherein in all modes of operation, a real part of an element of the data vector is stored before an imaginary part of the element of the data vector;  
       wherein in all modes of operation, a real part of an element of the coefficient vector is stored before an imaginary part of the element of the coefficient vector;  
       wherein in the first and second mode of operation, consecutive elements of the data vector are stored in consecutive odd memory words within data memory bank, and consecutive elements of the coefficients vector are stored in consecutive memory words within coefficient memory bank, in opposite order; and  
       wherein in the third mode of operation, consecutive elements of the data vector are stored in consecutive memory words within data memory bank, and consecutive elements of the coefficient vector are stored in consecutive memory words within coefficient memory bank.  
     
     
       2. A finite response impulse filter of claim  1  wherein the length of the data memory bank is double then the length of coefficient memory bank. 
     
     
       3. A finite response impulse filter of claim  1 , wherein the data address generator is comprising of: 
       a counter, coupled to the control unit and to the data memory;  
       a XOR gate, coupled to a least significant bit output of the counter and to the control unit;  
       a first multiplexer, coupled to the output of the XOR gate and to the control unit;  
       a second multiplexer, coupled to the XOR gate, to the control unit and to a second least significant output bit of the counter;  
       an AND gate, coupled to the control unit and to the output of the first multiplexer; and  
       wherein the address word signal, sent to the data memory bank is provided by the signals on the output of the AND gate, the second multiplexer and the outputs of the counter, which are not coupled to the second multiplexer or the XOR gate.  
     
     
       4. A finite response impulse filter of claim  3 , wherein the control unit sends the finite response impulse filter the following signals: 
       a first signal, which indicates that a real value element is fetched from a memory bank and a imaginary value elements is fetched simultaneously from the other memory bank;  
       a second signal which indicates that the coefficient vector is comprised of pure real value elements and data vector is comprised of complex elements;  
       a third signal which indicates that data vector stored within data memory bank is complex and that coefficient vector, stored in coefficient memory bank is pure real or pure imaginary or has alternating pure real and pure imaginary elements; and  
       a fourth signal which indicates that a data word has to be read.  
     
     
       5. A finite impulse response filter of claim  4 , wherein the first signal is inputted to an input of the XOR gate and to a data input of the first multiplexer; 
       wherein the second signal is inputted to the control input of the first multiplexer;  
       wherein the third signal is inputted to the control input of the second multiplexer and to an input of the AND gate; and  
       wherein the fourth signal is inputted to the input of the counter.  
     
     
       6. A method for finite response impulse filtering, comprising the following steps: 
       determining what is the mode of operation, according to the type of data vector and coefficient vector;  
       sending signals indicating the mode of operation;  
       storing consecutive elements of data vector in consecutive odd memory words of the data memory bank, and storing consecutive elements of coefficient vector in consecutive words of coefficient memory bank if the data vector and coefficient vector are pure real;  
       storing consecutive elements of data vector in consecutive odd memory words of the data memory bank, and storing consecutive elements of coefficient vector in consecutive words of coefficient memory bank if coefficient vector has alternating pure real and pure imaginary elements, and data vector is complex;  
       else, storing consecutive data vector elements in consecutive memory words of data memory bank and storing consecutive coefficient vector in consecutive memory words of coefficient memory bank; and  
       reading data vector elements and coefficient vector elements;  
       multiplying data vector elements by coefficient vector elements and summing the results of the multiplications.

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