Method for digital signal processing, DSP, mobile communication and audi o-device

Abstract

Embodiments of the present invention relate generally to digital signal processing. One embodiment contemplates a method for performing a digital signal processing operation having a first data word located at a misaligned starting address within a first memory. The method includes outputting the first data word to a register file during a first internal. During a second interval, the method further includes reading a second data word and a third data word from the first memory where the second data word is output to the register file and the third data word is output to the first buffer. Embodiments also contemplate a digital signal processor having a register filed capable of receiving one data word from a memory and one data word from a buffer during each of a series of processing intervals for performing a digital signal operation.

What is claimed is:  
     
       1. In a digital signal processor having a first memory, a first buffer, and a register file, a method for performing a digital signal processing operation having a first data word located at a misaligned starting address within the first memory, comprising: 
       outputting the first data word to the register file during a first interval;  
       during a second interval, reading a second data word and a third data word from the first memory, wherein the second data word is output to the register file and the third data word is output to the first buffer; and  
       completing the digital signal processing operation.  
     
     
       2. The method of claim  1 , further comprising: 
       during subsequent intervals, outputting to the register file two data words, wherein one of the two data words is read from the first buffer and the other one of the two data words is read from the first memory.  
     
     
       3. The method of claim  2 , further comprising: 
       during the subsequent intervals, accessing two data words stored within the register file in order to perform the digital signnl operation.  
     
     
       4. The method of claim  2 , wherein the digital signal processor comprises a second memory and a second buffer for providing another two data words to the register file. 
     
     
       5. The method of claim  4 , further comprising accessing two pairs of data words stored within the register file during the subsequent intervals, wherein one of the two pairs corresponds to the first memory, and the other one of the two pairs corresponds to the second memory. 
     
     
       6. The method of claim  2 , wherein the first and second intervals correspond to a first instruction and the subsequent intervals correspond to a second instruction. 
     
     
       7. The method of claim  1 , further comprising: 
       during subsequent intervals, accessing from the first memory a next pair of data words, wherein one of the next pair of data words is stored into the first buffer, and the other one of the next pair is stored into the register file.  
     
     
       8. The method of claim  7 , wherein the next pair of data words is a consecutive pair of data words. 
     
     
       9. The method of claim  7 , further comprising: 
       during the subsequent intervals, outputting to the register file two data words, wherein one of the two data words is read from the first buffer and the other one of the two data words is read from te first memory.  
     
     
       10. The method of claim  9 , wherein the two data words are consecutive data words. 
     
     
       11. The method of claim  9 , further comprsing: 
       during the subsequent intervals, accessing two data words stored within te register file in order to perform the digital signal operation.  
     
     
       12. The method of claim  11 , wherein the digital signal processor comprises a first multiplier and a first accumulator, and wherein the two data words accessed from the register file are output from the register file to the first multiplier for performing at least a portion of the digital signal processor operation. 
     
     
       13. The method of claim  7 , wherein the first and second intervals correspond to a first instruction and the subsequent intervals correspond to a second instruction. 
     
     
       14. The method of claim  1 , wherein the first memory includes even and odd addresses, and the misaligned starting address is an odd address. 
     
     
       15. A digital signal processor comprising: 
       an address generation unit;  
       a first memory coupled to the address generation unit;  
       a first buffer coupled to the first memory and capable of receiving data words from the first memory; and  
       a register file coupled to the fist memory and the first buffer, and capable of receiving one data word from the first memory and one data word from the first buffer during each of a plurality of processing intervals for performing a digital signal operation.  
     
     
       16. The digital signal processor of claim  15 , further comprising: 
       a second memory coupled to the address generation unit;  
       a second buffer coupled to the second memory and the register file, and capable of receiving data words from the second memory, wherein the register file is capable of receiving one data word from the second memory and one data word from the second buffer during each of the plurality of processing intervals.  
     
     
       17. The digital signal processor of claim  16 , further comprising: 
       a first multiplier coupled to the register file and capable of receiving from the register file two data words corresponding to the first memory and the first buffer, during one of the plurality of processing intervals; and  
       a second multiplier coupled to the register file and capable of receiving from the register file two data words corresponding to te second memory and the second buffer during the one of the plurality of processing intervals.  
     
     
       18. The digital signal processor of claim  17 , wherein the digital signal processor comprises only one address generation unit and is further characterized as being capable of performing two parallel multiplications on a set of four data words during a same time interval. 
     
     
       19. The digital signal processor of claim  16 , wherein the first memory and the second memory each include: 
       a storage array having even and odd addresses and capable of storing a plurality of consecutive data words.  
     
     
       20. The digital signal processor of claim  15 , wherein the digital signal processor is capable of performing a fist initialization interval if a starting address of the digital signal operation is an odd address. 
     
     
       21. The digital signal processor of claim  20 , wherein the first initialization interval stores a first data word into the register file, and a second initialization interval stores a second data word into the register file and a third data word into the first buffer. 
     
     
       22. The digital signal processor of claim  21 , wherein the first and second initialization intervals occur prior to the plurality of processing intervals.