Semiconductor device and a method of manufacturing the same

Abstract

In a semiconductor device of this invention, a pillar projection serving as a very thin active region is formed on the surface of a p-type silicon semiconductor substrate. A gate electrode 21 is formed to cover a central portion of the pillar projection. A pair of impurity diffusion layers 22 are formed on the pillar projection on the two sides of the gate electrode. An element isolation insulating film 23 is formed to sandwich and bury the side surfaces of the pillar projection. This semiconductor device has high performance equivalent to that of an SOI structure. The semiconductor device of this invention has three channels corresponding to a pair of a source and a drain, is selectively formed on the same semiconductor substrate as a common bulk transistor, and has a very fine structure and high drivability.

What is claimed is:  
     
       1. A semiconductor device comprising: 
       a gate electrode, a source, and a drain, wherein:  
       a surface of a semiconductor substrate is processed into a shape having a pillar projection which functions as an element active region,  
       said gate electrode is formed via a gate insulating film so as to cover a substantially central portion of a surface of said pillar projection,  
       said source and drain are formed by doping an impurity into portions of said pillar projection on two sides of said gate electrode,  
       an element isolation insulating film is formed on said semiconductor substrate to bury side surfaces of said pillar projection,  
       said gate electrode comprises an extension portion extending on said element isolation insulating film, said extension portion extends on said gate insulating film formed on the upper surface of said pillar projection, and lays across said pillar projection,  
       said gate electrode is formed between at least a part of side surfaces of said element isolation insulating film and said pillar projection, with in a space between side surfaces of said element isolation insulating film and a gate insulating film formed on the side surfaces of said pillar projection,  
       a buried insulating layer is formed in a predetermined portion of said pillar projection to cross said gate and divide said pillar projection into upper and lower portions, and  
       a portion of said pillar projection above said buried insulating layer is electrically isolated from said semiconductor substrate.  
     
     
       2. A semiconductor device, comprising: 
       a semiconductor substrate processed into a shape having an integrally formed pillar projection on a surface;  
       a conductive film formed by patterning via a first insulating film so as to cover a substantially central portion of a surface of said pillar projection;  
       a pair of diffusion regions formed by doping an impurity into portions of said pillar projection on two sides of said conductive film;  
       a second insulating film formed on said semiconductor substrate to bury side surfaces of said pillar projection;  
       said conductive film having an extension portion extending on said second insulating film; and  
       a buried insulating layer formed in a predetermined portion of said pillar projection to cross said conductive film and divide said pillar projection into upper and lower portions, wherein  
       a portion of said pillar projection above said buried insulating layer is electrically isolated from said semiconductor substrate.  
     
     
       3. A device according to claim  2 , wherein a height of the portion of said pillar projection above said buried insulating layer is not more than 0.1 μm. 
     
     
       4. A semiconductor device comprising: 
       a semiconductor substrate processed into a shape having an integrally formed pillar projection on a surface;  
       first and second conductive films formed via a first insulating film so as to cover substantially central portions of two side surfaces of said pillar projection and opposing each other while electrically isolated from each other;  
       a third conductive film formed via a second insulating film so as to cover a substantially central portion of an upper surface of said pillar projection and electrically isolated from said first and second conductive films;  
       a pair of diffusion regions formed by doping an impurity into portions of said pillar projection on two sides of said first, second, and third conductive films; and  
       a third insulating film formed on said semiconductor substrate to bury the side surfaces of said pillar projection.  
     
     
       5. A device according to claim  4 , wherein a thickness of said pillar projection is not more than 0.15 μm. 
     
     
       6. A device according to claim  4 , further comprising a side-wall insulating film between said third conductive film and said first and second conductive films. 
     
     
       7. A device according to claim  4 , wherein said third conductive film comprises an electric charge accumulation layer, an insulating film formed on said an electric charge accumulation layer, and a control gate electrode formed on said insulating film, said third conductive film and said pair of diffusion regions constituting a memory cell. 
     
     
       8. A device according to claim  7 , wherein said memory cell is a multi-valued memory cell storing data corresponding to a threshold value out of more than three different threshold values. 
     
     
       9. A device according to claim  4 , further comprising a capacitor comprising a lower electrode, a dielectric film formed on said lower electrode, and an upper electrode formed on said dielectric film, wherein said lower electrode is connected to one of said pair of diffusion regions. 
     
     
       10. A semiconductor device comprising: 
       a semiconductor substrate processed into a shape having an integrally formed pillar projection on a surface;  
       first and second conductive films formed via a first insulating film to cover substantially central portions of two side surfaces of said pillar projection and opposing each other while electrically isolated from each other via said first insulating film and said pillar projection;  
       diffusion regions formed by doping an impurity into an upper surface region of said pillar projection and a surface region of said semiconductor substrate below said first and second conductive films formed via said first insulating film;  
       a third conductive film electrically connected to said diffusion region formed in the upper surface region of said pillar projection;  
       a side-wall insulating film between said third conductive film and said first and second conductive films; and  
       a second insulating film formed on said semiconductor substrate to bury the side surfaces of said pillar projection.  
     
     
       11. A device according to claim  10 , wherein a width of said first and second conductive films is substantially the same as a width of said pillar projection. 
     
     
       12. A device according to claim  10 , wherein a thickness of said pillar projection is not more than 0.15 μm. 
     
     
       13. A semiconductor device comprising a semiconductor substrate and first, second, and third transistors having first, second, and third gate electrodes and a source and a drain shared by said first, second, and third gate electrodes, wherein 
       said semiconductor substrate is processed into a shape having a pillar projection which functions as an element active region on a surface,  
       said first and second gate electrodes are formed via a first gate insulating film so as to cover substantially central portions of two side surfaces of said pillar projection and oppose each other while electrically isolated from each other,  
       said third gate electrode is formed via a second gate insulating film so as to cover a substantially central portion of an upper surface of said pillar projection and electrically isolated from said first and second gate electrodes,  
       said source and drain are formed by doping an impurity into portions of said pillar projection on two sides of said first, second, and third gate electrodes, and  
       an element isolation insulating film is formed on said semiconductor substrate to bury side surfaces of said pillar projection.  
     
     
       14. A device according to claim  13 , wherein said first and second gate insulating films are the same thermal oxide film. 
     
     
       15. A device according to claim  13 , further comprising a side-wall insulating film between said third gate electrode and said first and second gate electrodes. 
     
     
       16. A device according to claim  13 , wherein said third conductive film comprises an electric charge accumulation layer, an insulating film formed on said an electric charge accumulation layer, and a control gate electrode formed on said insulating film, said third conductive film and said source and drain constituting a memory cell. 
     
     
       17. A device according to claim  16 , wherein said memory cell is a multi-valued memory cell storing data corresponding to a threshold value out of more than three different threshold values. 
     
     
       18. A device according to claim  13 , further comprising a capacitor comprising a lower electrode, a dielectric film formed on said lower electrode, and an upper electrode formed on said dielectric film, wherein said lower electrode is connected to one of said source and said drain. 
     
     
       19. A semiconductor device comprising a semiconductor substrate and first and second transistors having first and second gate electrodes and a source and a drain shared by said first and second gate electrodes, wherein 
       said semiconductor substrate is processed into a shape having a pillar projection which functions as an element active region on a surface,  
       said first and second gate electrodes are formed via a gate insulating film so as to cover a substantially central portion of a surface of said pillar projection and oppose each other while electrically isolated from each other,  
       said source is formed by doping an impurity into a surface region of said semiconductor substrate below said pillar projection,  
       said drain is formed by doping an impurity into an upper surface region of said pillar projection,  
       an interconnecting film electrically connected to said drain formed in the upper surface region of said pillar projection;  
       a side-wall insulating film between said interconnecting film and said first and second gate electrodes; and  
       an element isolation insulating film is formed on said semiconductor substrate to bury side surfaces of said pillar projection.  
     
     
       20. A storage medium storing, in a computer readable form, individual steps of an operation of determining multi-valued storage information stored in a semiconductor device according to claim  8 . 
     
     
       21. A storage medium storing, in a computer readable form, individual steps of an operation of determining multi-valued storage information stored in a semiconductor device according to claim  17 . 
     
     
       22. A semiconductor device comprising: 
       a semiconductor substrate processed into a shape having an integrally formed pillar projection on a surface;  
       first and second conductive films formed via a first insulating film so as to cover substantially central portions of two side surfaces of said pillar projection and opposing each other while electrically isolated from each other via said first insulating film and said pillar projection;  
       diffusion regions formed by doping an impurity into an upper surface region of said pillar projection and a surface region of said semiconductor substrate below said first and second conductive films formed via said first insulating film;  
       a second insulating film formed on said semiconductor substrate to bury the side surfaces of said pillar projection; and  
       a third insulating film formed by patterning on an upper surface of said pillar projection.  
     
     
       23. A device according to claim  22 , wherein a width of said first and second conductive films is substantially the same as a width of said pillar projection. 
     
     
       24. A device according to claim  22 , wherein a thickness of said pillar projection is not more than 0.15 μm.