Output circuit for semiconductor integrated circuit

Abstract

An output circuit for a semiconductor integrated circuit includes an output terminal, a first NMOS transistor having one end of a current path between a drain and a source thereof connected to a first node, having a control signal input a gate thereof, and having the other end of the current path connected to a ground potential node, a second NMOS transistor having one end of a current path between a drain and a source thereof connected to the first node and the other end connected to an output terminal, a PMOS transistor and an NMOS transistor connected between a second node that is a gate of the second NMOS transistor and the output terminal, to act as capacitance elements, and a pull-up element connected between the second node and the node of the power potential.

What is claimed is:  
     
       1. An output circuit for a semiconductor integrated circuit, comprising: 
       a signal output terminal;  
       an N-channel first MOS transistor having a current path between a drain and a source thereof, and a gate, one end of the current path being connected to a ground potential node, and the gate being supplied with a first control signal;  
       a first node connected to the other end of the current path of the first MOS transistor;  
       an N-channel second MOS transistor, having a current path between a drain and a source thereof, and a gate, one end of the current path being connected to the first node and the other end being connected to the signal output terminal;  
       a second node connected to the gate of the second MOS transistor connected thereto;  
       a capacitance element connected between the second node and the signal output terminal;  
       a first power node to which a first power potential is supplied; and  
       a first pull-up element connected between the second node and the first power node.  
     
     
       2. The circuit according to claim  1 , further comprising: 
       a second power node being supplied with a potential higher than the power potential; and  
       a second pull-up element connected between the second power node and the signal output terminal.  
     
     
       3. The circuit according to claim  1 , wherein the first pull-up element comprises a P-channel first MOS transistor having a current path between a drain and a source thereof and a gate, the current path being connected between the first power node and the second node, the gate being connected to one of the first node, the ground potential node, and the signal output terminal. 
     
     
       4. The circuit according to claim  1 , wherein the first pull-up element is a resistance element. 
     
     
       5. The circuit according to claim  4 , wherein the resistance element is formed of a P-type diffusion layer provided in an N-type semiconductor substrate connected to the first power node, and a pn junction diode is parasitically formed between the P-type diffusion layer and the N-type semiconductor substrate. 
     
     
       6. The circuit according to claim  1 , further comprising a P-channel first MOS transistor having a current path between a drain and a source thereof and a gate, the current path being connected between the first power node and the second node, the gate being supplied with the first control signal. 
     
     
       7. The circuit according to claim  1 , further comprising a pn junction diode having an anode and a cathode, the anode being connected to the second node, the cathode being connected to the first power node. 
     
     
       8. The circuit according to claim  1 , wherein the capacitance element includes a P-channel first MOS transistor having a drain, a source, a gate, and a back gate, the gate being connected to the second node, the drain, source, and back gate being all connected to the signal output terminal. 
     
     
       9. The circuit according to claim  1 , wherein the capacitance element includes an N-channel third MOS transistor having a drain, a source, a gate, and a back gate, the gate being connected to the second node, the drain and source both being connected to the signal output terminal, the back gate being connected to the ground potential node. 
     
     
       10. The circuit according to claim  1 , further comprising a P-channel first MOS transistor having a current path between a drain and a source thereof, and a gate, one end of the current path being connected to the signal output terminal, the other end of the current path being connected to the first power node, and the gate being supplied with the first control signal. 
     
     
       11. The circuit according to claim  1 , further comprising a P-channel first MOS transistor having a current path between a drain and a source thereof, and a gate, one end of the current path being connected to the signal output terminal, the other end of the current path being connected to the first power node, the gate being supplied with a second control signal. 
     
     
       12. The circuit according to claim  1 , further comprising an input circuit connected to the first node to obtain an input signal from the first node to provide it to another circuit. 
     
     
       13. An output circuit for a semiconductor integrated circuit, comprising: 
       a signal output terminal;  
       an N-channel first MOS transistor having a current path being between a drain and a source thereof, and a gate, one end of the current path being connected to a ground potential node, and the gate being supplied with a first control signal;  
       a first node connected to the other end of the current path of the first MOS transistor;  
       an N-channel second MOS transistor having a current path between a drain and a source thereof, and a gate, one end of the current path being connected to the first node and the other end being connected to the signal output terminal;  
       a second node connected to the gate of the second MOS transistor;  
       a capacitance element connected between the first node and the second node;  
       a first power node to which a first power potential is supplied; and  
       a first pull-up element connected between the second node and the first power node.  
     
     
       14. The circuit according to claim  13 , further comprising: 
       a second power node being supplied with a potential higher than the power potential; and  
       a second pull-up element connected between the second power node and the signal output terminal.  
     
     
       15. The circuit according to claim  13 , wherein the first pull-up element comprises a P-channel first MOS transistor having a current path between a drain and a source thereof and a gate, the current path being connected between the first power node and the second node, the gate being connected to one of the first node, the ground potential node, and the signal output terminal. 
     
     
       16. The circuit according to claim  13 , wherein the first pull-up element is a resistance element. 
     
     
       17. The circuit according to claim  16 , wherein the resistance element is formed of a P-type diffusion layer provided in an N-type semiconductor substrate connected to the first power node, and a pn junction diode is parasitically formed between the P-type diffusion layer and the N-type semiconductor substrate. 
     
     
       18. The circuit according to claim  13 , further comprising a P-channel first MOS transistor having a current path between a drain and a source thereof and a gate, the current path being connected between the first power node and the second node, the gate being supplied with the first control signal. 
     
     
       19. The circuit according to claim  13 , further comprising a pn junction diode having an anode and a cathode, the anode being connected to the second node, the cathode being connected to the first power node. 
     
     
       20. The circuit according to claim  13 , wherein the capacitance element includes a P-channel first MOS transistor having a drain, a source, a gate, and a back gate, the gate being connected to the first node, the drain, source, and back gate being all connected to the second node. 
     
     
       21. The circuit according to claim  14 , wherein the capacitance element includes an N-channel third MOS transistor having a drain, a source, a gate, and a back gate, the gate being connected to the second node, the drain and source both being connected to the first node, the back gate being connected to the ground potential node. 
     
     
       22. The circuit according to claim  13 , further comprising a P-channel first MOS transistor having a current path between a drain and a source thereof, and a gate, one end of the current path being connected to the signal output terminal, the other end of the current path being connected to the first power node, and the gate being supplied with the first control signal. 
     
     
       23. The circuit according to claim  13 , further comprising a P-channel first MOS transistor having a current path between a drain and a source thereof, and a gate, one end of the current path being connected to the signal output terminal, the other end of the current path being connected to the first power node, and the gate being supplied with a second control signal. 
     
     
       24. The circuit according to claim  13 , further comprising an input circuit connected to the first node to obtain an input signal from the first node to provide it to another circuit.