Method for fabricating a DRAM cell capacitor using hemispherical grain (HSG) silicon

Abstract

A stacked DRAM cell capacitor having HSG silicon only on a top portion of a storage node, not on a bottom portion thereof. The storage node has a double layer structure including a bottom layer and a top layer. The bottom layer is made of a conductive material that suppresses the growth of HSG seeds. Accordingly, electrical bridges between adjacent storage nodes, particularly at a bottom portion, can be prevented.

What is claimed is:  
     
       1. A method for fabricating a DRAM cell capacitor on an integrated circuit substrate, the substrate having an interlayer insulating layer thereon, contact plugs being separately buried in the interlayer insulating layer for electrically contacting the substrate, the method comprising: 
       forming a first conductive layer on the interlayer insulating layer and on the contact plugs;  
       etching selected portions of the first conductive layer between the contact plugs, thereby forming a first conductive pattern electrically connected to the contact plugs;  
       forming a second conductive layer on the interlayer insulating layer and on the first conductive pattern;  
       etching selected portions of the second conductive layer, thereby forming a second conductive pattern, the first and second conductive patterns defining a storage node;  
       selectively forming an HSG silicon layer on the second conductive pattern;  
       forming a dielectric film on the entire surface of the semiconductor substrate; and  
       forming a plate node on the dielectric film.  
     
     
       2. The method according to claim  1 , wherein the first conductive layer is formed to a thickness in the range from 1,000 angstroms to 2,000 angstroms. 
     
     
       3. The method according to claim  1 , wherein the distance between adjacent first conductive patterns is about 1,300 angstroms or less. 
     
     
       4. The method according to claim  1 , wherein the first conductive layer is made of a conductive material that suppresses the growth of HSG seeds thereon. 
     
     
       5. The method according to claim  4 , wherein the first conductive layer is formed of polysilicon. 
     
     
       6. The method according to claim  4 , wherein the step of forming a first conductive layer comprises the steps of: 
       depositing an amorphous silicon layer on the interlayer insulating layer and on the contact plugs; and  
       annealing the amorphous silicon layer, thereby transforming the amorphous silicon layer into the first conductive layer that suppresses the growth of HSG seeds thereon.  
     
     
       7. The method according to claim  4 , wherein the step of forming a first conductive layer comprises depositing an amorphous silicon layer on the interlayer insulating layer and on the contact plugs, wherein the step of etching selected portions of the first conductive layer comprises etching selected portions of the amorphous silicon layer between the contact plugs, thereby forming an amorphous silicon layer pattern electrically connected to the contact plugs, the method further comprising: 
       annealing the amorphous silicon layer pattern, thereby transforming the amorphous silicon layer pattern into the first conductive pattern that suppresses the growth of HSG seeds thereon.  
     
     
       8. The method according to claim  6 , wherein the annealing is carried out in a nitrogen ambient at a temperature of about 750° C. for about 10 minutes. 
     
     
       9. The method according to claim  7 , wherein the annealing is carried out in a nitrogen ambient at a temperature of about 750° C. for about 10 minutes. 
     
     
       10. The method according to claim  1 , wherein the second conductive layer is formed to a thickness greater than the thickness of the first conductive layer. 
     
     
       11. A method for fabricating a DRAM cell capacitor comprising: 
       depositing an interlayer insulating layer on a semiconductor substrate;  
       etching selected portions of the interlayer insulating layer to form contact hole exposing the substrate;  
       depositing a first conductive layer in the contact holes and on the interlayer insulating layer;  
       planarizing the first conductive layer;  
       etching the first conductive layer between the contact holes to form a first conductive pattern;  
       depositing a second conductive layer on the first conductive pattern and on the interlayer insulating layer;  
       etching selected portions of the second conductive layer to form a second conductive pattern, the first and second conductive patterns defining a storage node;  
       selectively forming an HSG silicon layer on the second conductive pattern;  
       forming a dielectric film on the entire surface of the semiconductor substrate; and  
       forming a plate node on the dielectric film.  
     
     
       12. The method according to claim  11 , wherein the first conductive pattern has a predetermined thickness in the range from 1,000 angstroms to 2,000 angstroms. 
     
     
       13. The method according to claim  11 , wherein the first conductive layer is made of a conductive material that suppresses the growth of HSG seeds thereon. 
     
     
       14. The method according to claim  13 , wherein the first conductive layer is formed of polysilicon. 
     
     
       15. The method according to claim  13 , wherein the step of depositing a first conductive layer comprises: 
       depositing an amorphous silicon layer in the contact holes and on the interlayer insulating layer; and  
       annealing the amorphous silicon layer, thereby transforming the amorphous silicon layer into the first conductive layer that suppresses the growth of HSG seeds thereon.  
     
     
       16. The method according to claim  13 , wherein the step of depositing a first conductive layer comprises depositing an amorphous silicon layer on the contact holes and on the interlayer insulating layer, wherein the step of etching the first conductive layer between the contact holes comprises etching the amorphous silicon layer between the contact holes to form an amorphous silicon layer pattern, the method further comprising: 
       annealing the amorphous silicon layer pattern, thereby transforming the amorphous silicon layer pattern into the first conductive pattern that suppresses the growth of HSG silicon thereon.  
     
     
       17. The method according to claim  15 , wherein the annealing is carried out in a nitrogen ambient at a temperature of about 750° C. for about 10 minutes. 
     
     
       18. The method according to claim  16 , wherein the annealing is carried out in a nitrogen ambient at a temperature of about 750° C. for about 10 minutes. 
     
     
       19. The method according to claim  11 , wherein the distance between adjacent first conductive patterns is about 1,300 angstroms or less. 
     
     
       20. The method according to claim  11 , wherein the second conductive layer is formed to a thickness greater than the thickness of the first conductive layer. 
     
     
       21. The method according to claim  11 , the dielectric film is formed of Ta 2 O 5 .